Texas-instruments TMS320C67X/C67X+ DSP Uživatelský manuál

TMS320C67x/C67x+ DSPCPU and Instruction SetReference GuideLiterature Number: SPRU733May 2005

Contentsx SPRU733Contents4.2.11 MPYI Instruction 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ABSDP Absolute Value, Double-Precision Floating-Point3-40 Instruction Set SPRU733Absolute Value, Double-Precision Floating-PointABSDPSyntax ABSDP (.

Absolute Value, Double-Precision Floating-Point ABSDP3-41 Instruction SetSPRU733Pipeline StageE1 E2Read src2_lsrc2_hWritten dst_l dst_hUnit in use.SI

ABSSP Absolute Value, Single-Precision Floating-Point3-42 Instruction Set SPRU733Absolute Value, Single-Precision Floating-PointABSSPSyntax ABSSP (.

Absolute Value, Single-Precision Floating-Point ABSSP3-43 Instruction SetSPRU733Pipeline StageE1Read src2Written dstUnit in use.SInstruction Type Sin

ADD Add Two Signed Integers Without Saturation3-44 Instruction Set SPRU733Add Two Signed Integers Without SaturationADDSyntax ADD (.unit) src1, src2

Add Two Signed Integers Without Saturation ADD3-45 Instruction SetSPRU733Opcode .S unit31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0creg z dst src2

ADD Add Two Signed Integers Without Saturation3-46 Instruction Set SPRU733Opcode .D unit31 292827 2322 1817 1312 76543210creg z dst src2 src1 op 1 0

Add Two Signed Integers Without Saturation ADD3-47 Instruction SetSPRU733Example 1 ADD .L2X A1,B1,B2Before instruction 1 cycle after instructionA1000

ADDAB Add Using Byte Addressing Mode3-48 Instruction Set SPRU733Add Using Byte Addressing ModeADDABSyntax ADDAB (.unit) src2, src1, dst.unit = .D1 o

Add Using Byte Addressing Mode ADDAB3-49 Instruction SetSPRU733Example 1 ADDAB .D1 A4,A2,A4Before instruction 1 cycle after instructionA20000 000BhA2

ContentsxiContentsSPRU733A Instruction Compatibility A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADDAD Add Using Doubleword Addressing Mode3-50 Instruction Set SPRU733Add Using Doubleword Addressing ModeADDADSyntax ADDAD (.unit) src2, src1, dst.

Add Using Doubleword Addressing Mode ADDAD3-51 Instruction SetSPRU733Instruction Type Single-cycleDelay Slots 0Functional UnitLatency1See Also ADD, A

ADDAH Add Using Halfword Addressing Mode3-52 Instruction Set SPRU733Add Using Halfword Addressing ModeADDAHSyntax ADDAH (.unit) src2, src1, dst.unit

Add Using Halfword Addressing Mode ADDAH3-53 Instruction SetSPRU733Example 1 ADDAH .D1 A4,A2,A4Before instruction 1 cycle after instructionA20000 000

ADDAW Add Using Word Addressing Mode3-54 Instruction Set SPRU733Add Using Word Addressing ModeADDAWSyntax ADDAW (.unit) src2, src1, dst.unit = .D1 o

Add Using Word Addressing Mode ADDAW3-55 Instruction SetSPRU733Example 1 ADDAW .D1 A4,2,A4Before instruction 1 cycle after instructionA40002 0000hA4

ADDDP Add Two Double-Precision Floating-Point Values3-56 Instruction Set SPRU733Add Two Double-Precision Floating-Point ValuesADDDPSyntax ADDDP (.un

Add Two Double-Precision Floating-Point Values ADDDP3-57 Instruction SetSPRU733Notes:1) This instruction takes the rounding mode from and sets the wa

ADDDP Add Two Double-Precision Floating-Point Values3-58 Instruction Set SPRU733Pipeline StageE1 E2 E3 E4 E5 E6 E7Read src1_lsrc2_lsrc1_hsrc2_hWritt

Add Signed 16-Bit Constant to Register ADDK3-59 Instruction SetSPRU733Add Signed 16-Bit Constant to RegisterADDKSyntax ADDK (.unit) cst, dst.unit = .

Figuresxii SPRU733FiguresFigures1−1 TMS320C67x DSP Block Diagram 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADDSP Add Two Single-Precision Floating-Point Values3-60 Instruction Set SPRU733Add Two Single-Precision Floating-Point ValuesADDSPSyntax ADDSP (.un

Add Two Single-Precision Floating-Point Values ADDSP3-61 Instruction SetSPRU733Notes:1) This instruction takes the rounding mode from and sets the wa

ADDSP Add Two Single-Precision Floating-Point Values3-62 Instruction Set SPRU733Pipeline StageE1 E2 E3 E4Read src1src2Written dstUnit in use.L or .S

Add Two Unsigned Integers Without Saturation ADDU3-63 Instruction SetSPRU733Add Two Unsigned Integers Without SaturationADDUSyntax ADDU (.unit) src1,

ADDU Add Two Unsigned Integers Without Saturation3-64 Instruction Set SPRU733Example 1 ADDU .L1 A1,A2,A5:A4Before instruction 1 cycle after instruct

Add Two 16-Bit Integers on Upper and Lower Register Halves ADD23-65 Instruction SetSPRU733Add Two 16-Bit Integers on Upper and Lower Register HalvesA

ADD2 Add Two 16-Bit Integers on Upper and Lower Register Halves3-66 Instruction Set SPRU733Execution if (cond) {msb16(src1) + msb16(src2) → msb16(ds

Bitwise AND AND3-67 Instruction SetSPRU733Bitwise ANDANDSyntax AND (.unit) src1, src2, dst.unit = .L1, .L2, .S1, .S2Compatibility C62x, C64x, C67x, a

AND Bitwise AND3-68 Instruction Set SPRU733Pipeline StageE1Read src1, src2Written dstUnit in use.L or .SInstruction Type Single-cycleDelay Slots 0Se

Branch Using a Displacement B3-69 Instruction SetSPRU733Branch Using a DisplacementBSyntax B (.unit) label.unit = .S1 or .S2Compatibility C62x, C64x,

FiguresxiiiFiguresSPRU7334−18 Two-Cycle DP Instruction Phases 4-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B Branch Using a Displacement3-70 Instruction Set SPRU733Target InstructionPipeline StageE1 PSPW PR DP DC E1ReadWrittenBranchTakenUnit in use.SInst

Branch Using a Register B3-71 Instruction SetSPRU733Branch Using a RegisterBSyntax B (.unit) src2.unit = .S2Compatibility C62x, C64x, C67x, and C67x+

B Branch Using a Register3-72 Instruction Set SPRU733Target InstructionPipeline StageE1 PSPW PR DP DC E1Read src2WrittenBranchTakenUnit in use.S2In

Branch Using an Interrupt Return Pointer B IRP3-73 Instruction SetSPRU733Branch Using an Interrupt Return PointerB IRPSyntax B (.unit) IRP.unit = .S2

B IRP Branch Using an Interrupt Return Pointer3-74 Instruction Set SPRU733Target InstructionPipeline StageE1 PSPW PR DP DC E1Read IRPWrittenBranchTa

Branch Using NMI Return Pointer B NRP3-75 Instruction SetSPRU733Branch Using NMI Return PointerB NRPSyntax B (.unit) NRP.unit = .S2Compatibility C62x

B NRP Branch Using NMI Return Pointer3-76 Instruction Set SPRU733Target InstructionPipeline StageE1 PSPW PR DP DC E1Read NRPWrittenBranchTakenUnit

Clear a Bit Field CLR3-77 Instruction SetSPRU733Clear a Bit FieldCLRSyntax CLR (.unit) src2, csta, cstb, dstorCLR (.unit) src2, src1, dst.unit = .S1

CLR Clear a Bit Field3-78 Instruction Set SPRU733Description The field in src2, specified by csta and cstb, is cleared to zero. csta and cstbmay be

Clear a Bit Field CLR3-79 Instruction SetSPRU733Example 1 CLR .S1 A1,4,19,A2Before instruction 1 cycle after instructionA107A4 3F2AhA1 07A4 3F2AhA2 x

Tablesxiv SPRU733TablesTables1−1 Typical Applications for the TMS320 DSPs 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMPEQ Compare for Equality, Signed Integers3-80 Instruction Set SPRU733Compare for Equality, Signed IntegersCMPEQSyntax CMPEQ (.unit) src1, src2, ds

Compare for Equality, Signed Integers CMPEQ3-81 Instruction SetSPRU733Pipeline StageE1Read src1, src2Written dstUnit in use.LInstruction Type Single-

CMPEQDP Compare for Equality, Double-Precision Floating-Point Values3-82 Instruction Set SPRU733Compare for Equality, Double-Precision Floating-Poin

Compare for Equality, Double-Precision Floating-Point Values CMPEQDP3-83 Instruction SetSPRU733Notes:1) In the case of NaN compared with itself, the

CMPEQSP Compare for Equality, Single-Precision Floating-Point Values3-84 Instruction Set SPRU733Compare for Equality, Single-Precision Floating-Poin

Compare for Equality, Single-Precision Floating-Point Values CMPEQSP3-85 Instruction SetSPRU733Notes:1) In the case of NaN compared with itself, the

CMPGT Compare for Greater Than, Signed Integers3-86 Instruction Set SPRU733Compare for Greater Than, Signed IntegersCMPGTSyntax CMPGT (.unit) src1,

Compare for Greater Than, Signed Integers CMPGT3-87 Instruction SetSPRU733Description Performs a signed comparison of src1 to src2. If src1 is greate

CMPGT Compare for Greater Than, Signed Integers3-88 Instruction Set SPRU733Example 1 CMPGT .L1X A1,B1,A2Before instruction 1 cycle after instruction

Compare for Greater Than, Double-Precision Floating-Point Values CMPGTDP3-89 Instruction SetSPRU733Compare for Greater Than, Double-Precision Floatin

TablesxvTablesSPRU7333−19 Data Types Supported by LDH(U) Instruction 3-131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−20 D

CMPGTDP Compare for Greater Than, Double-Precision Floating-Point Values (C67x CPU)3-90 Instruction Set SPRU733Note:No configuration bits other than

Compare for Greater Than, Single-Precision Floating-Point Values CMPGTSP3-91 Instruction SetSPRU733Compare for Greater Than, Single-Precision Floatin

CMPGTSP Compare for Greater Than, Single-Precision Floating-Point Values3-92 Instruction Set SPRU733Note:No configuration bits other than those show

Compare for Greater Than, Unsigned Integers CMPGTU3-93 Instruction SetSPRU733Compare for Greater Than, Unsigned IntegersCMPGTUSyntax CMPGTU (.unit) s

CMPGTU Compare for Greater Than, Unsigned Integers3-94 Instruction Set SPRU733Pipeline StageE1Read src1, src2Written dstUnit in use.LInstruction Typ

Compare for Less Than, Signed Integers CMPLT3-95 Instruction SetSPRU733Compare for Less Than, Signed IntegersCMPLTSyntax CMPLT (.unit) src1, src2, ds

CMPLT Compare for Less Than, Signed Integers3-96 Instruction Set SPRU733Description Performs a signed comparison of src1 to src2. If src1 is less th

Compare for Less Than, Signed Integers CMPLT3-97 Instruction SetSPRU733Example 1 CMPLT .L1 A1,A2,A3Before instruction 1 cycle after instructionA10000

CMPLTDP Compare for Less Than, Double-Precision Floating-Point Values3-98 Instruction Set SPRU733Compare for Less Than, Double-Precision Floating-Po

Compare for Less Than, Double-Precision Floating-Point Values CMPLTDP3-99 Instruction SetSPRU733Note:No configuration bits other than those above are

Tablesxvi SPRU733Tables5−1 Interrupt Priorities 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMPLTSP Compare for Less Than, Single-Precision Floating-Point Values3-100 Instruction Set SPRU733Compare for Less Than, Single-Precision Floating-P

Compare for Less Than, Single-Precision Floating-Point Values CMPLTSP3-101 Instruction SetSPRU733Note:No configuration bits other than those above ar

CMPLTU Compare for Less Than, Unsigned Integers3-102 Instruction Set SPRU733Compare for Less Than, Unsigned IntegersCMPLTUSyntax CMPLTU (.unit) src1

Compare for Less Than, Unsigned Integers CMPLTU3-103 Instruction SetSPRU733Pipeline StageE1Read src1, src2Written dstUnit in use.LInstruction Type Si

DPINT Convert Double-Precision Floating-Point Value to Integer3-104 Instruction Set SPRU733Convert Double-Precision Floating-Point Value to IntegerD

Convert Double-Precision Floating-Point Value to Integer DPINT3-105 Instruction SetSPRU733Pipeline StageE1 E2 E3 E4Read src2_lsrc2_hWritten dstUnit i

DPSP Convert Double-Precision Floating-Point Value to Single-Precision Floating-Point Value3-106 Instruction Set SPRU733Convert Double-Precision Flo

Convert Double-Precision Floating-Point Value to Single-Precision Floating-Point Value DPSP3-107 Instruction SetSPRU7337) If underflow occurs, the IN

DPTRUNC Convert Double-Precision Floating-Point Value to Integer With Truncation3-108 Instruction Set SPRU733Convert Double-Precision Floating-Point

Convert Double-Precision Floating-Point Value to Integer With Truncation DPTRUNC3-109 Instruction SetSPRU733Pipeline StageE1 E2 E3 E4Read src2_lsrc2_

ExamplesxviiExamplesSPRU733Examples3−1 Fully Serial p-Bit Pattern in a Fetch Packet 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EXT Extract and Sign-Extend a Bit Field3-110 Instruction Set SPRU733Extract and Sign-Extend a Bit FieldEXTSyntax EXT (.unit) src2, csta, cstb, dstor

Extract and Sign-Extend a Bit Field EXT3-111 Instruction SetSPRU733Description The field in src2, specified by csta and cstb, is extracted and sign-e

EXT Extract and Sign-Extend a Bit Field3-112 Instruction Set SPRU733Instruction Type Single-cycleDelay Slots 0See Also EXTUExample 1 EXT .S1 A1,10,1

Extract and Zero-Extend a Bit Field EXTU3-113 Instruction SetSPRU733Extract and Zero-Extend a Bit FieldEXTUSyntax EXTU (.unit) src2, csta, cstb, dsto

EXTU Extract and Zero-Extend a Bit Field3-114 Instruction Set SPRU733Description The field in src2, specified by csta and cstb, is extracted and zer

Extract and Zero-Extend a Bit Field EXTU3-115 Instruction SetSPRU733Instruction Type Single-cycleDelay Slots 0See Also EXTExample 1 EXTU .S1 A1,10,19

IDLE Multicycle NOP With No Termination Until Interrupt3-116 Instruction Set SPRU733Multicycle NOP With No Termination Until InterruptIDLESyntax IDL

Convert Signed Integer to Double-Precision Floating-Point Value INTDP3-117 Instruction SetSPRU733Convert Signed Integer to Double-Precision Floating-

INTDP Convert Signed Integer to Double-Precision Floating-Point Value3-118 Instruction Set SPRU733Example INTDP .L1x B4,A1:A0Before instruction 5 c

Convert Unsigned Integer to Double-Precision Floating-Point Value INTDPU3-119 Instruction SetSPRU733Convert Unsigned Integer to Double-Precision Floa

1-1IntroductionSPRU733aIntroductionThe TMS320C6000™ digital signal processor (DSP) platform is part of theTMS320™ DSP family. The TMS320C62x™ DSP gene

INTDPU Convert Unsigned Integer to Double-Precision Floating-Point Value3-120 Instruction Set SPRU733Example INTDPU .L1 A4,A1:A0Before instruction 5

Convert Signed Integer to Single-Precision Floating-Point Value INTSP3-121 Instruction SetSPRU733Convert Signed Integer to Single-Precision Floating-

INTSPU Convert Unsigned Integer to Single-Precision Floating-Point Value3-122 Instruction Set SPRU733Convert Unsigned Integer to Single-Precision Fl

Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDB(U)3-123 Instruction SetSPRU733Load Byte From Memory With a 5-Bit U

LDB(U) Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset3-124 Instruction Set SPRU733The addressing arithmetic that per

Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDB(U)3-125 Instruction SetSPRU733Example LDB .D1 *−A5[4],A7Before LDB

LDB(U) Load Byte From Memory With a 15-Bit Unsigned Constant Offset3-126 Instruction Set SPRU733Load Byte From Memory With a 15-Bit Unsigned Constan

Load Byte From Memory With a 15-Bit Unsigned Constant Offset LDB(U)3-127 Instruction SetSPRU733Execution if (cond) mem → dstelse nopNote:This instruc

LDDW Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset3-128 Instruction Set SPRU733Load Doubleword From Memory With an

Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset LDDW3-129 Instruction SetSPRU733Increments and decrements default to

TMS320 DSP Family OverviewIntroduction1-2 SPRU7331.1 TMS320 DSP Family OverviewThe TMS320™ DSP family consists of fixed-point, floating-point, and mul

LDDW Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset3-130 Instruction Set SPRU733Delay Slots 4Functional UnitLatency

Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDH(U)3-131 Instruction SetSPRU733Load Halfword From Memory With a

LDH(U) Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset3-132 Instruction Set SPRU733The addressing arithmetic that

Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDH(U)3-133 Instruction SetSPRU733Example LDH .D1 *++A4[A1],A8Befo

LDH(U) Load Halfword From Memory With a 15-Bit Unsigned Constant Offset3-134 Instruction Set SPRU733Load Halfword From Memory With a 15-Bit Unsigned

Load Halfword From Memory With a 15-Bit Unsigned Constant Offset LDH(U)3-135 Instruction SetSPRU733Table 3−20. Data Types Supported by LDH(U) Instruc

LDW Load Word From Memory With a 5-Bit Unsigned Constant Offset or Register Offset3-136 Instruction Set SPRU733Load Word From Memory With a 5-Bit Un

Load Word From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDW3-137 Instruction SetSPRU733Increments and decrements default to 1

LDW Load Word From Memory With a 5-Bit Unsigned Constant Offset or Register Offset3-138 Instruction Set SPRU733Example 1 LDW .D1 *A10,B1Before LDW 1

Load Word From Memory With a 15-Bit Unsigned Constant Offset LDW3-139 Instruction SetSPRU733Load Word From Memory With a 15-Bit Unsigned Constant Off

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections,modifications, enhancements, improvemen

TMS320C6000 DSP Family Overview1-3IntroductionSPRU733Table 1−1. Typical Applications for the TMS320 DSPsAutomotive Consumer ControlAdaptive ride contr

LDW Load Word From Memory With a 15-Bit Unsigned Constant Offset3-140 Instruction Set SPRU733Pipeline StageE1 E2 E3 E4 E5Read B14 / B15Written dstUn

Leftmost Bit Detection LMBD3-141 Instruction SetSPRU733Leftmost Bit DetectionLMBDSyntax LMBD (.unit) src1, src2, dst.unit = .L1 or .L2Compatibility C

LMBD Leftmost Bit Detection3-142 Instruction Set SPRU733Execution if (cond) {if (src10 == 0) lmb0(src2) → dstif (src10 == 1) lmb1(src2) → dst}else n

Multiply Signed 16 LSB x Signed 16 LSB MPY3-143 Instruction SetSPRU733Multiply Signed 16 LSB  Signed 16 LSBMPYSyntax MPY (.unit) src1, src2, dst.uni

MPY Multiply Signed 16 LSB x Signed 16 LSB3-144 Instruction Set SPRU733Example 1 MPY .M1 A1,A2,A3Before instruction 2 cycles after instructionA10000

Multiply Two Double-Precision Floating-Point Values MPYDP3-145 Instruction SetSPRU733Multiply Two Double-Precision Floating-Point ValuesMPYDPSyntax M

MPYDP Multiply Two Double-Precision Floating-Point Values3-146 Instruction Set SPRU733Pipeline StageE1 E2 E3 E4 E5 E6 E7 E8 E9 E10Read src1_lsrc2_ls

Multiply Signed 16 MSB x Signed 16 MSB MPYH3-147 Instruction SetSPRU733Multiply Signed 16 MSB  Signed 16 MSBMPYHSyntax MPYH (.unit) src1, src2, dst.

MPYH Multiply Signed 16 MSB x Signed 16 MSB3-148 Instruction Set SPRU733Example MPYH .M1 A1,A2,A3Before instruction 2 cycles after instructionA10023

Multiply Signed 16 MSB x Signed 16 LSB MPYHL3-149 Instruction SetSPRU733Multiply Signed 16 MSB  Signed 16 LSBMPYHLSyntax MPYHL (.unit) src1, src2, d

TMS320C67x DSP Features and OptionsIntroduction1-4 SPRU7331.3 TMS320C67x DSP Features and Options The C6000 devices execute up to eight 32-bit instru

MPYHL Multiply Signed 16 MSB x Signed 16 LSB3-150 Instruction Set SPRU733Example MPYHL .M1 A1,A2,A3Before instruction 2 cycles after instructionA100

Multiply Unsigned 16 MSB x Unsigned 16 LSB MPYHLU3-151 Instruction SetSPRU733Multiply Unsigned 16 MSB  Unsigned 16 LSBMPYHLUSyntax MPYHLU (.unit) sr

MPYHSLU Multiply Signed 16 MSB x Unsigned 16 LSB3-152 Instruction Set SPRU733Multiply Signed 16 MSB  Unsigned 16 LSBMPYHSLUSyntax MPYHSLU (.unit) s

Multiply Signed 16 MSB x Unsigned 16 MSB MPYHSU3-153 Instruction SetSPRU733Multiply Signed 16 MSB  Unsigned 16 MSBMPYHSUSyntax MPYHSU (.unit) src1,

MPYHU Multiply Unsigned 16 MSB x Unsigned 16 MSB3-154 Instruction Set SPRU733Multiply Unsigned 16 MSB  Unsigned 16 MSBMPYHUSyntax MPYHU (.unit) src

Multiply Unsigned 16 MSB x Signed 16 LSB MPYHULS3-155 Instruction SetSPRU733Multiply Unsigned 16 MSB  Signed 16 LSBMPYHULSSyntax MPYHULS (.unit) src

MPYHUS Multiply Unsigned 16 MSB x Signed 16 MSB3-156 Instruction Set SPRU733Multiply Unsigned 16 MSB  Signed 16 MSBMPYHUSSyntax MPYHUS (.unit) src1

Multiply 32-Bit x 32-Bit Into 32-Bit Result MPYI3-157 Instruction SetSPRU733Multiply 32-Bit  32-Bit Into 32-Bit ResultMPYISyntax MPYI (.unit) src1,

MPYI Multiply 32-Bit x 32-Bit Into 32-Bit Result3-158 Instruction Set SPRU733Functional UnitLatency4See Also MPYIDExampleMPYI .M1X A1,B2,A3Before in

Multiply 32-Bit x 32-Bit Into 64-Bit Result MPYID3-159 Instruction SetSPRU733Multiply 32-Bit  32-Bit Into 64-Bit ResultMPYIDSyntax MPYID (.unit) src

TMS320C67x DSP Features and Options1-5IntroductionSPRU73340-bit arithmetic options add extra precision for vocoders and othercomputationally intensiv

MPYID Multiply 32-Bit x 32-Bit Into 64-Bit Result3-160 Instruction Set SPRU733Functional UnitLatency4See Also MPYIExampleMPYID .M1 A1,A2,A5:A4Before

Multiply Signed 16 LSB x Signed 16 MSB MPYLH3-161 Instruction SetSPRU733Multiply Signed 16 LSB  Signed 16 MSBMPYLHSyntax MPYLH (.unit) src1, src2, d

MPYLH Multiply Signed 16 LSB x Signed 16 MSB3-162 Instruction Set SPRU733Example MPYLH .M1 A1,A2,A3Before instruction 2 cycles after instructionA109

Multiply Unsigned 16 LSB x Unsigned 16 MSB MPYLHU3-163 Instruction SetSPRU733Multiply Unsigned 16 LSB  Unsigned 16 MSBMPYLHUSyntax MPYLHU (.unit) sr

MPYLSHU Multiply Signed 16 LSB x Unsigned 16 MSB3-164 Instruction Set SPRU733Multiply Signed 16 LSB  Unsigned 16 MSBMPYLSHUSyntax MPYLSHU (.unit) s

Multiply Unsigned 16 LSB x Signed 16 MSB MPYLUHS3-165 Instruction SetSPRU733Multiply Unsigned 16 LSB  Signed 16 MSBMPYLUHSSyntax MPYLUHS (.unit) src

MPYSP Multiply Two Single-Precision Floating-Point Values3-166 Instruction Set SPRU733Multiply Two Single-Precision Floating-Point ValuesMPYSPSyntax

Multiply Two Single-Precision Floating-Point Values MPYSP3-167 Instruction SetSPRU733Pipeline StageE1 E2 E3 E4Read src1src2Written dstUnit in use.MIf

MPYSPDP Multiply Single-Precision Value x Double-Precision Value (C67x+ CPU)3-168 Instruction Set SPRU733Multiply Single-Precision Floating-Point Va

Multiply Single-Precision Value x Double-Precision Value (C67x+ CPU) MPYSPDP3-169 Instruction SetSPRU733Pipeline StageE1 E2 E3 E4 E5 E6 E7Read src1sr

TMS320C67x DSP Features and OptionsIntroduction1-6 SPRU733The VelociTI architecture of the C6000 platform of devices make them the firstoff-the-shelf

MPYSP2DP Multiply Two Single-Precision Floating-Point Values for Double-Precision Result (C67x+ CPU)3-170 Instruction Set SPRU733Multiply Two Single

Multiply Two Single-Precision Floating-Point Values for Double-Precision Result (C67x+ CPU) MPYSP2DP3-171 Instruction SetSPRU733Pipeline StageE1 E2 E

MPYSU Multiply Signed 16 LSB x Unsigned 16 LSB3-172 Instruction Set SPRU733Multiply Signed 16 LSB  Unsigned 16 LSBMPYSUSyntax MPYSU (.unit) src1, s

Multiply Signed 16 LSB x Unsigned 16 LSB MPYSU3-173 Instruction SetSPRU733See Also MPY, MPYU, MPYUSExampleMPYSU .M1 13,A1,A2Before instruction 2 cycl

MPYU Multiply Unsigned 16 LSB x Unsigned 16 LSB3-174 Instruction Set SPRU733Multiply Unsigned 16 LSB  Unsigned 16 LSBMPYUSyntax MPYU (.unit) src1,

Multiply Unsigned 16 LSB x Unsigned 16 LSB MPYU3-175 Instruction SetSPRU733Example MPYU .M1 A1,A2,A3Before instruction 2 cycles after instructionA100

MPYUS Multiply Unsigned 16 LSB x Signed 16 LSB3-176 Instruction Set SPRU733Multiply Unsigned 16 LSB  Signed 16 LSBMPYUSSyntax MPYUS (.unit) src1, s

Multiply Unsigned 16 LSB x Signed 16 LSB MPYUS3-177 Instruction SetSPRU733Example MPYUS .M1 A1,A2,A3Before instruction 2 cycles after instructionA112

MV Move From Register to Register3-178 Instruction Set SPRU733Move From Register to RegisterMVSyntax MV (.unit) src2, dst.unit = .L1, .L2, .S1, .S2,

Move From Register to Register MV3-179 Instruction SetSPRU733Opcode .D unit31 292827 2322 1817 1312 76543210creg z dst src2 0 0 0 0 0 0 1 0 0 1 0 1 0

TMS320C67x DSP Architecture1-7IntroductionSPRU7331.4 TMS320C67x DSP ArchitectureFigure 1−1 is the block diagram for the C67x DSP. The C6000 devices co

MVC Move Between Control File and Register File3-180 Instruction Set SPRU733Move Between Control File and Register FileMVCSyntax MVC (.unit) src2, d

Move Between Control File and Register File MVC3-181 Instruction SetSPRU733Execution if (cond) src2 → dstelse nopNote:The MVC instruction executes on

MVC Move Between Control File and Register File3-182 Instruction Set SPRU733Table 3−21. Register Addresses for Accessing the Control RegistersAcrony

Move Signed Constant Into Register and Sign Extend MVK3-183 Instruction SetSPRU733Move Signed Constant Into Register and Sign ExtendMVKSyntax MVK (.u

MVK Move Signed Constant Into Register and Sign Extend3-184 Instruction Set SPRU733Instruction Type Single cycleDelay Slots 0See Also MVKH, MVKL, MV

Move 16-Bit Constant Into Upper Bits of Register MVKH/MVKLH3-185 Instruction SetSPRU733Move 16-Bit Constant Into Upper Bits of RegisterMVKH/MVKLHSynt

MVKH/MVKLH Move 16-Bit Constant Into Upper Bits of Register3-186 Instruction Set SPRU733Instruction Type Single-cycleDelay Slots 0Note:Use the MVK i

Move Signed Constant Into Register and Sign Extend−Used with MVKH MVKL3-187 Instruction SetSPRU733Move Signed Constant Into Register and Sign ExtendM

MVKL Move Signed Constant Into Register and Sign Extend−Used with MVKH3-188 Instruction Set SPRU733Pipeline StageE1ReadWritten dstUnit in use.SInstr

Negate NEG3-189 Instruction SetSPRU733NegateNEGSyntax NEG (.unit) src2, dst.unit = .L1, .L2, .S1, .S2Compatibility C62x, C64x, C67x, and C67x+ CPUOpc

TMS320C67x DSP ArchitectureIntroduction1-8 SPRU7331.4.1 Central Processing Unit (CPU)The C67x CPU, in Figure 1−1, is common to all the C62x/C64x/C67x

NOP No Operation3-190 Instruction Set SPRU733No OperationNOPSyntax NOP [count].unit = noneCompatibility C62x, C64x, C67x, and C67x+ CPUOpcode31 18 1

No Operation NOP3-191 Instruction SetSPRU733Example 1 NOPMVK .S1 125h,A1Before NOP1 cycle after NOP(No operationexecutes)1 cycle after MVKA11234

NORM Normalize Integer3-192 Instruction Set SPRU733Normalize IntegerNORMSyntax NORM (.unit) src2, dst.unit = .L1 or .L2Compatibility C62x, C64x, C67

Normalize Integer NORM3-193 Instruction SetSPRU733Execution if (cond) norm(src) → dstelse nopPipeline StageE1Read src2Written dstUnit in use.LInstruc

NOT Bitwise NOT3-194 Instruction Set SPRU733Bitwise NOTNOTSyntax NOT (.unit) src2, dst.unit = .L1, .L2, .S1, .S2Compatibility C62x, C64x, C67x, and

Bitwise OR OR3-195 Instruction SetSPRU733Bitwise ORORSyntax OR (.unit) src1, src2, dst.unit = .L1, .L2, .S1, .S2Compatibility C62x, C64x, C67x, and C

OR Bitwise OR3-196 Instruction Set SPRU733Execution if (cond) src1 OR src2 → dstelse nopPipeline StageE1Read src1, src2Written dstUnit in use.L or .

Double-Precision Floating-Point Reciprocal Approximation RCPDP3-197 Instruction SetSPRU733Double-Precision Floating-Point Reciprocal ApproximationRCP

RCPDP Double-Precision Floating-Point Reciprocal Approximation3-198 Instruction Set SPRU733Note:1) If src2 is SNaN, NaN_out is placed in dst and the

Single-Precision Floating-Point Reciprocal Approximation RCPSP3-199 Instruction SetSPRU733Single-Precision Floating-Point Reciprocal ApproximationRCP

TMS320C67x DSP Architecture1-9IntroductionSPRU733DMA Controller (C6701 DSP only) transfers data between address rangesin the memory map without inter

RCPSP Single-Precision Floating-Point Reciprocal Approximation3-200 Instruction Set SPRU733Notes:1) If src2 is SNaN, NaN_out is placed in dst and th

Double-Precision Floating-Point Square-Root Reciprocal Approximation RSQRDP3-201 Instruction SetSPRU733Double-Precision Floating-Point Square-Root Re

RSQRDP Double-Precision Floating-Point Square-Root Reciprocal Approximation3-202 Instruction Set SPRU733Notes:1) If src2 is SNaN, NaN_out is placed

Single-Precision Floating-Point Square-Root Reciprocal Approximation RSQRSP3-203 Instruction SetSPRU733Single-Precision Floating-Point Square-Root Re

RSQRSP Single-Precision Floating-Point Square-Root Reciprocal Approximation3-204 Instruction Set SPRU733Note:1) If src2 is SNaN, NaN_out is placed i

Add Two Signed Integers With Saturation SADD3-205 Instruction SetSPRU733Add Two Signed Integers With SaturationSADDSyntax SADD (.unit) src1, src2, ds

SADD Add Two Signed Integers With Saturation3-206 Instruction Set SPRU733Pipeline StageE1Read src1, src2Written dstUnit in use.LInstruction Type Sin

Add Two Signed Integers With Saturation SADD3-207 Instruction SetSPRU733Example 3 SADD .L1X B2,A5:A4,A7:A6Before instruction 1 cycle after instructio

SAT Saturate a 40-Bit Integer to a 32-Bit Integer3-208 Instruction Set SPRU733Saturate a 40-Bit Integer to a 32-Bit IntegerSATSyntax SAT (.unit) src

Saturate a 40-Bit Integer to a 32-Bit Integer SAT3-209 Instruction SetSPRU733Example 1 SAT .L2 B1:B0,B5Before instruction 1 cycle after instruction 2

2-1CPU Data Paths and ControlSPRU733CPU Data Paths and ControlThis chapter focuses on the CPU, providing information about the data paths andcontrol r

SET Set a Bit Field3-210 Instruction Set SPRU733Set a Bit FieldSETSyntax SET (.unit) src2, csta, cstb, dstorSET (.unit) src2, src1, dst.unit = .S1 o

Set a Bit Field SET3-211 Instruction SetSPRU733Description The field in src2, specified by csta and cstb, is set to all 1s. The csta and cstboperands

SET Set a Bit Field3-212 Instruction Set SPRU733Example 1 SET .S1 A0,7,21,A1Before instruction 1 cycle after instructionA04B13 4A1EhA0 4B13 4A1EhA1

Arithmetic Shift Left SHL3-213 Instruction SetSPRU733Arithmetic Shift LeftSHLSyntax SHL (.unit) src2, src1, dst.unit = .S1 or .S2Compatibility C62x,

SHL Arithmetic Shift Left3-214 Instruction Set SPRU733Pipeline StageE1Read src1, src2Written dstUnit in use.SInstruction Type Single-cycleDelay Slot

Arithmetic Shift Right SHR3-215 Instruction SetSPRU733Arithmetic Shift RightSHRSyntax SHR (.unit) src2, src1, dst.unit = .S1 or .S2Compatibility C62x

SHR Arithmetic Shift Right3-216 Instruction Set SPRU733Pipeline StageE1Read src1, src2Written dstUnit in use.SInstruction Type Single-cycleDelay Slo

Logical Shift Right SHRU3-217 Instruction SetSPRU733Logical Shift RightSHRUSyntax SHRU (.unit) src2, src1, dst.unit = .S1 or .S2Compatibility C62x, C

SHRU Logical Shift Right3-218 Instruction Set SPRU733Pipeline StageE1Read src1, src2Written dstUnit in use.SInstruction Type Single-cycleDelay Slots

Multiply Signed 16 LSB x Signed 16 LSB With Left Shift and Saturation SMPY3-219 Instruction SetSPRU733Multiply Signed 16 LSB  Signed 16 LSB With Lef

IntroductionCPU Data Paths and Control2-2 SPRU7332.1 IntroductionThe components of the data path for the TMS320C67x CPU are shown inFigure 2−1. These

SMPY Multiply Signed 16 LSB x Signed 16 LSB With Left Shift and Saturation3-220 Instruction Set SPRU733Example SMPY .M1 A1,A2,A3Before instruction 2

Multiply Signed 16 MSB x Signed 16 MSB With Left Shift and Saturation SMPYH3-221 Instruction SetSPRU733Multiply Signed 16 MSB  Signed 16 MSB With Le

SMPYHL Multiply Signed 16 MSB x Signed 16 LSB With Left Shift and Saturation3-222 Instruction Set SPRU733Multiply Signed 16 MSB  Signed 16 LSB With

Multiply Signed 16 MSB x Signed 16 LSB With Left Shift and Saturation SMPYHL3-223 Instruction SetSPRU733Example SMPYHL .M1 A1,A2,A3Before instruction

SMPYLH Multiply Signed 16 LSB x Signed 16 MSB With Left Shift and Saturation3-224 Instruction Set SPRU733Multiply Signed 16 LSB  Signed 16 MSB With

Multiply Signed 16 LSB x Signed 16 MSB With Left Shift and Saturation SMPYLH3-225 Instruction SetSPRU733Example SMPYLH .M1 A1,A2,A3Before instruction

SPDP Convert Single-Precision Floating-Point Value to Double-Precision Floating-Point Value3-226 Instruction Set SPRU733Convert Single-Precision Flo

Convert Single-Precision Floating-Point Value to Double-Precision Floating-Point Value SPDP3-227 Instruction SetSPRU733Pipeline StageE1 E2Read src2Wr

SPINT Convert Single-Precision Floating-Point Value to Integer3-228 Instruction Set SPRU733Convert Single-Precision Floating-Point Value to IntegerS

Convert Single-Precision Floating-Point Value to Integer SPINT3-229 Instruction SetSPRU733Pipeline StageE1 E2 E3 E4Read src2Written dstUnit in use.LI

General-Purpose Register Files2-3CPU Data Paths and ControlSPRU733Figure 2−1. TMS320C67x CPU Data Paths882X1X.L2.S2.M2.D2(B0−B15)(A0−A15).D1.M1.S1.L1l

SPTRUNC Convert Single-Precision Floating-Point Value to Integer With Truncation3-230 Instruction Set SPRU733Convert Single-Precision Floating-Point

Convert Single-Precision Floating-Point Value to Integer With Truncation SPTRUNC3-231 Instruction SetSPRU733Pipeline StageE1 E2 E3 E4Read src2Written

SSHL Shift Left With Saturation3-232 Instruction Set SPRU733Shift Left With SaturationSSHLSyntax SSHL (.unit) src2, src1, dst.unit = .S1 or .S2Compa

Shift Left With Saturation SSHL3-233 Instruction SetSPRU733Pipeline StageE1Read src1, src2Written dstUnit in use.SInstruction Type Single-cycleDelay

SSUB Subtract Two Signed Integers With Saturation3-234 Instruction Set SPRU733Subtract Two Signed Integers With SaturationSSUBSyntax SSUB (.unit) sr

Subtract Two Signed Integers With Saturation SSUB3-235 Instruction SetSPRU733Pipeline StageE1Read src1, src2Written dstUnit in use.LInstruction Type

STB Store Byte to Memory With a 5-Bit Unsigned Constant Offset or Register Offset3-236 Instruction Set SPRU733Store Byte to Memory With a 5-Bit Unsi

Store Byte to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STB3-237 Instruction SetSPRU733Increments and decrements default to 1 a

STB Store Byte to Memory With a 15-Bit Unsigned Constant Offset3-238 Instruction Set SPRU733Store Byte to Memory With a 15-Bit Unsigned Constant Off

Store Byte to Memory With a 15-Bit Unsigned Constant Offset STB3-239 Instruction SetSPRU733Pipeline StageE1Read B14/B15, srcWrittenUnit in use.D2Inst

iiiRead This FirstSPRU733PrefaceRead This FirstAbout This ManualThe TMS320C6000™ digital signal processor (DSP) platform is part of theTMS320™ DSP fam

General-Purpose Register FilesCPU Data Paths and Control2-4 SPRU733Table 2−1. 40-Bit/64-Bit Register PairsRegister FilesA BDevicesA1:A0 B1:B0 C67x DSP

STH Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset3-240 Instruction Set SPRU733Store Halfword to Memory With a 5-

Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STH3-241 Instruction SetSPRU733Increments and decrements default to

STH Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset3-242 Instruction Set SPRU733Example 2 STH .D1 A1,*A10−−[A11]Be

Store Halfword to Memory With a 15-Bit Unsigned Constant Offset STH3-243 Instruction SetSPRU733Store Halfword to Memory With a 15-Bit Unsigned Consta

STH Store Halfword to Memory With a 15-Bit Unsigned Constant Offset3-244 Instruction Set SPRU733Pipeline StageE1Read B14/B15, srcWrittenUnit in use.

Store Word to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STW3-245 Instruction SetSPRU733Store Word to Memory With a 5-Bit Unsign

STW Store Word to Memory With a 5-Bit Unsigned Constant Offset or Register Offset3-246 Instruction Set SPRU733Increments and decrements default to 1

Store Word to Memory With a 15-Bit Unsigned Constant Offset STW3-247 Instruction SetSPRU733Store Word to Memory With a 15-Bit Unsigned Constant Offse

STW Store Word to Memory With a 15-Bit Unsigned Constant Offset3-248 Instruction Set SPRU733Pipeline StageE1Read B14/B15, srcWrittenUnit in use.D2In

Subtract Two Signed Integers Without Saturation SUB3-249 Instruction SetSPRU733Subtract Two Signed Integers Without SaturationSUBSyntax SUB (.unit) s

Functional Units2-5CPU Data Paths and ControlSPRU7332.3 Functional UnitsThe eight functional units in the C6000 data paths can be divided into twogrou

SUB Subtract Two Signed Integers Without Saturation3-250 Instruction Set SPRU733Opcode .S unit31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0creg z d

Subtract Two Signed Integers Without Saturation SUB3-251 Instruction SetSPRU733Opcode .D unit31 292827 2322 1817 1312 76543210creg z dst src2 src1 op

SUB Subtract Two Signed Integers Without Saturation3-252 Instruction Set SPRU733Instruction Type Single-cycleDelay Slots 0See Also ADD, SSUB, SUBC,

Subtract Using Byte Addressing Mode SUBAB3-253 Instruction SetSPRU733Subtract Using Byte Addressing ModeSUBABSyntax SUBAB (.unit) src2, src1, dst.uni

SUBAB Subtract Using Byte Addressing Mode3-254 Instruction Set SPRU733Example SUBAB .D1 A5,A0,A5Before instruction 1 cycle after instructionA00000 0

Subtract Using Halfword Addressing Mode SUBAH3-255 Instruction SetSPRU733Subtract Using Halfword Addressing ModeSUBAHSyntax SUBAH (.unit) src2, src1,

SUBAW Subtract Using Word Addressing Mode3-256 Instruction Set SPRU733Subtract Using Word Addressing ModeSUBAWSyntax SUBAW (.unit) src2, src1, dst.u

Subtract Using Word Addressing Mode SUBAW3-257 Instruction SetSPRU733Example SUBAW .D1 A5,2,A3Before instruction 1 cycle after instructionA3xxxx xxxx

SUBC Subtract Conditionally and Shift−Used for Division3-258 Instruction Set SPRU733Subtract Conditionally and Shift—Used for DivisionSUBCSyntax SUB

Subtract Conditionally and Shift−Used for Division SUBC3-259 Instruction SetSPRU733Example 1 SUBC .L1 A0,A1,A0Before instruction 1 cycle after instru

Register File Cross PathsCPU Data Paths and Control2-6 SPRU7332.4 Register File Cross PathsEach functional unit reads directly from and writes directl

SUBDP Subtract Two Double-Precision Floating-Point Values3-260 Instruction Set SPRU733Subtract Two Double-Precision Floating-Point ValuesSUBDPSyntax

Subtract Two Double-Precision Floating-Point Values SUBDP3-261 Instruction SetSPRU733Notes:1) This instruction takes the rounding mode from and sets

SUBDP Subtract Two Double-Precision Floating-Point Values3-262 Instruction Set SPRU733Pipeline StageE1 E2 E3 E4 E5 E6 E7Read src1_lsrc2_lsrc1_hsrc2_

Subtract Two Single-Precision Floating-Point Values SUBSP3-263 Instruction SetSPRU733Subtract Two Single-Precision Floating-Point ValuesSUBSPSyntax S

SUBSP Subtract Two Single-Precision Floating-Point Values3-264 Instruction Set SPRU733Notes:1) This instruction takes the rounding mode from and set

Subtract Two Single-Precision Floating-Point Values SUBSP3-265 Instruction SetSPRU733Pipeline StageE1 E2 E3 E4Read src1src2Written dstUnit in use.LIn

SUBU Subtract Two Unsigned Integers Without Saturation3-266 Instruction Set SPRU733Subtract Two Unsigned Integers Without SaturationSUBUSyntax SUBU

Subtract Two Unsigned Integers Without Saturation SUBU3-267 Instruction SetSPRU733Example SUBU .L1 A1,A2,A5:A4Before instruction 1 cycle after instru

SUB2 Subtract Two 16-Bit Integers on Upper and Lower Register Halves3-268 Instruction Set SPRU733Subtract Two 16-Bit Integers on Upper and Lower Reg

Subtract Two 16-Bit Integers on Upper and Lower Register Halves SUB23-269 Instruction SetSPRU733Execution if (cond) {(lsb16(src1) − lsb16(src2)) → ls

Data Address Paths2-7CPU Data Paths and ControlSPRU7332.6 Data Address PathsThe data address paths (DA1 and DA2) are each connected to the .D units in

XOR Bitwise Exclusive OR3-270 Instruction Set SPRU733Bitwise Exclusive ORXORSyntax XOR (.unit) src1, src2, dst.unit = .L1, .L2, .S1, .S2Compatibili

Bitwise Exclusive OR XOR3-271 Instruction SetSPRU733Execution if (cond) src1 XOR src2 → dstelse nopPipeline StageE1Read src1, src2Written dstUnit in

ZERO Zero a Register3-272 Instruction Set SPRU733Zero a RegisterZEROSyntax ZERO (.unit) dst.unit = .L1, .L2, .D1, .D2, .S1, .S2Compatibility C62x, C

4-1PipelineSPRU733PipelineThe C67x DSP pipeline provides flexibility to simplify programming andimprove performance. Two factors provide this flexibil

Pipeline Operation OverviewPipeline4-2 SPRU7334.1 Pipeline Operation OverviewThe pipeline phases are divided into three stages: Fetch Decode Execut

Pipeline Operation Overview4-3PipelineSPRU733Figure 4−2. Fetch Phases of the PipelinePRPWPSPGPWMemoryPSPRPGRegistersunitsFunctional(a)(b)CPUPRPWPSPG25

Pipeline Operation OverviewPipeline4-4 SPRU733Figure 4−3(a) shows the decode phases in sequential order from left to right.Figure 4−3(b) shows a fetch

Pipeline Operation Overview4-5PipelineSPRU7334.1.3 ExecuteThe execute portion of the pipeline is subdivided into ten phases (E1−E10),as compared to th

Pipeline Operation OverviewPipeline4-6 SPRU7334.1.4 Pipeline Operation SummaryFigure 4−5 shows all the phases in each stage of the C67x DSP pipeline i

Pipeline Operation Overview4-7PipelineSPRU733Table 4−1. Operations Occurring During Pipeline Phases Stage Phase Symbol During This PhaseInstructionTy

Control Register FileCPU Data Paths and Control2-8 SPRU7332.7.1 Register Addresses for Accessing the Control RegistersTable 2−4 lists the register add

Pipeline Operation OverviewPipeline4-8 SPRU733Table 4−1. Operations Occurring During Pipeline Phases (Continued)StageInstructionTypeCompletedDuring T

Pipeline Operation Overview4-9PipelineSPRU733Table 4−1. Operations Occurring During Pipeline Phases (Continued)StageInstructionTypeCompletedDuring Th

Pipeline Operation OverviewPipeline4-10 SPRU733Registers used by the instructions in E1 are shaded in Figure 4−7. The multi-plexers used for the input

Pipeline Operation Overview4-11PipelineSPRU733Many C67x DSP instructions are single-cycle instructions, which means theyhave only one execution phase

Pipeline Execution of Instruction TypesPipeline4-12 SPRU7334.2 Pipeline Execution of Instruction TypesThe pipeline operation of the C67x DSP instructi

Pipeline Execution of Instruction Types4-13PipelineSPRU733Table 4−2. Execution Stage Length Description for Each Instruction Type (Continued)Instructi

Pipeline Execution of Instruction TypesPipeline4-14 SPRU733Table 4−2. Execution Stage Length Description for Each Instruction Type (Continued)Instruct

Pipeline Execution of Instruction Types4-15PipelineSPRU733Table 4−2. Execution Stage Length Description for Each Instruction Type (Continued)Instructi

Pipeline Execution of Instruction TypesPipeline4-16 SPRU7334.2.1 Single-Cycle InstructionsSingle-cycle instructions complete execution during the E1 p

Pipeline Execution of Instruction Types4-17PipelineSPRU7334.2.2 16 y 16-Bit Multiply InstructionsThe 16 × 16-bit multiply instructions use both the E1

Control Register File2-9CPU Data Paths and ControlSPRU7332.7.2 Pipeline/Timing of Control Register AccessesAll MVC instructions are single-cycle instr

Pipeline Execution of Instruction TypesPipeline4-18 SPRU7334.2.3 Store InstructionsStore instructions require phases E1 through E3 of the pipeline to

Pipeline Execution of Instruction Types4-19PipelineSPRU733Figure 4−13. Store Instruction Execution Block DiagramMemoryE2E3Memory controllerRegister fi

Pipeline Execution of Instruction TypesPipeline4-20 SPRU7334.2.4 Load InstructionsData loads require five, E1−E5, of the pipeline execute phases to co

Pipeline Execution of Instruction Types4-21PipelineSPRU733Figure 4−15. Load Instruction Execution Block DiagramE5AddressE3MemoryE2E4Memory controllerR

Pipeline Execution of Instruction TypesPipeline4-22 SPRU7334.2.5 Branch InstructionsAlthough branch takes one execute phase, there are five delay slot

Pipeline Execution of Instruction Types4-23PipelineSPRU733Figure 4−17. Branch Instruction Execution Block DiagramDPPRPWPSPG3232323232323232256NOPMVSMP

Pipeline Execution of Instruction TypesPipeline4-24 SPRU7334.2.6 Two-Cycle DP InstructionsTwo-cycle DP instructions use both the E1 and E2 phases of t

Pipeline Execution of Instruction Types4-25PipelineSPRU7334.2.7 Four-Cycle InstructionsFour-cycle instructions use the E1 through E4 phases of the pip

Pipeline Execution of Instruction TypesPipeline4-26 SPRU7334.2.8 INTDP InstructionThe INTDP instruction uses the E1 through E5 phases of the pipeline

Pipeline Execution of Instruction Types4-27PipelineSPRU7334.2.9 DP Compare InstructionsThe DP compare instructions use the E1 and E2 phases of the pip

Control Register FileCPU Data Paths and Control2-10 SPRU7332.7.3 Addressing Mode Register (AMR)For each of the eight registers (A4–A7, B4–B7) that can

Pipeline Execution of Instruction TypesPipeline4-28 SPRU7334.2.10 ADDDP/SUBDP Instructions The ADDDP/SUBDP instructions use the E1 through E7 phases o

Pipeline Execution of Instruction Types4-29PipelineSPRU7334.2.11 MPYI InstructionThe MPYI instruction uses the E1 through E9 phases of the pipeline to

Pipeline Execution of Instruction TypesPipeline4-30 SPRU7334.2.12 MPYID InstructionThe MPYID instruction uses the E1 through E10 phases of the pipelin

Pipeline Execution of Instruction Types4-31PipelineSPRU7334.2.13 MPYDP InstructionThe MPYDP instruction uses the E1 through E10 phases of the pipeline

Pipeline Execution of Instruction TypesPipeline4-32 SPRU7334.2.14 MPYSPDP InstructionThe MPYSPDP instruction uses the E1 through E7 phases of the pipe

Functional Unit Constraints4-33PipelineSPRU7334.2.15 MPYSP2DP InstructionThe MPYSP2DP instruction uses the E1 through E5 phases of the pipeline tocomp

Functional Unit ConstraintsPipeline4-34 SPRU7334.3.1 .S-Unit ConstraintsTable 4−18 shows the instruction constraints for single-cycle instructionsexec

Functional Unit Constraints4-35PipelineSPRU733Table 4−19 shows the instruction constraints for DP compare instructionsexecuting on the .S unit.Table 4

Functional Unit ConstraintsPipeline4-36 SPRU733Table 4−20 shows the instruction constraints for 2-cycle DP instructions exe-cuting on the .S unit.Tabl

Functional Unit Constraints4-37PipelineSPRU733Table 4−21 shows the instruction constraints for ADDSP/SUBSP instructionsexecuting on the .S unit.Table

Control Register File2-11CPU Data Paths and ControlSPRU733Table 2−5. Addressing Mode Register (AMR) Field Descriptions (Continued)Bit DescriptionValue

Functional Unit ConstraintsPipeline4-38 SPRU733Table 4−22 shows the instruction constraints for ADDDP/SUBDP instructionsexecuting on the .S unit.Table

Functional Unit Constraints4-39PipelineSPRU733Table 4−23 shows the instruction constraints for branch instructions executingon the .S unit.Table 4−23.

Functional Unit ConstraintsPipeline4-40 SPRU7334.3.2 .M-Unit ConstraintsTable 4−24 shows the instruction constraints for 16 × 16 multiply instructions

Functional Unit Constraints4-41PipelineSPRU733Table 4−25 shows the instruction constraints for 4-cycle instructions executingon the .M unit.Table 4−25

Functional Unit ConstraintsPipeline4-42 SPRU733Table 4−26 shows the instruction constraints for MPYI instructions executingon the .M unit.Table 4−26.

Functional Unit Constraints4-43PipelineSPRU733Table 4−27 shows the instruction constraints for MPYID instructions executingon the .M unit.Table 4−27.

Functional Unit ConstraintsPipeline4-44 SPRU733Table 4−28 shows the instruction constraints for MPYDP instructionsexecuting on the .M unit.Table 4−28.

Functional Unit Constraints4-45PipelineSPRU733Table 4−29 shows the instruction constraints for MPYSP instructionsexecuting on the .M unit.Table 4−29.

Functional Unit ConstraintsPipeline4-46 SPRU733Table 4−30 shows the instruction constraints for MPYSPDP instructionsexecuting on the .M unit.Table 4−3

Functional Unit Constraints4-47PipelineSPRU733Table 4−31 shows the instruction constraints for MPYSP2DP instructionsexecuting on the .M unit.Table 4−3

Control Register FileCPU Data Paths and Control2-12 SPRU733Table 2−5. Addressing Mode Register (AMR) Field Descriptions (Continued)Bit DescriptionValu

Functional Unit ConstraintsPipeline4-48 SPRU7334.3.3 .L-Unit ConstraintsTable 4−32 shows the instruction constraints for single-cycle instructionsexec

Functional Unit Constraints4-49PipelineSPRU733Table 4−33 shows the instruction constraints for 4-cycle instructions executingon the .L unit.Table 4−33

Functional Unit ConstraintsPipeline4-50 SPRU733Table 4−34 shows the instruction constraints for INTDP instructions executingon the .L unit.Table 4−34.

Functional Unit Constraints4-51PipelineSPRU733Table 4−35 shows the instruction constraints for ADDDP/SUBDP instructionsexecuting on the .L unit.Table

Functional Unit ConstraintsPipeline4-52 SPRU7334.3.4 .D-Unit Instruction ConstraintsTable 4−36 shows the instruction constraints for load instructions

Functional Unit Constraints4-53PipelineSPRU733Table 4−37 shows the instruction constraints for store instructions executingon the .D unit.Table 4−37.

Functional Unit ConstraintsPipeline4-54 SPRU733Table 4−38 shows the instruction constraints for single-cycle instructionsexecuting on the .D unit.Tabl

Functional Unit Constraints4-55PipelineSPRU733Table 4−39 shows the instruction constraints for LDDW instructions executingon the .D unit.Table 4−39. L

Performance ConsiderationsPipeline4-56 SPRU7334.4 Performance ConsiderationsThe C67x DSP pipeline is most effective when it is kept as full as the alg

Performance Considerations4-57PipelineSPRU733Figure 4−28. Pipeline Operation: Fetch Packets With Different Numbers of Execute PacketsClock cycleFetchp

Control Register File2-13CPU Data Paths and ControlSPRU7332.7.4 Control Status Register (CSR)The control status register (CSR) contains control and st

Performance ConsiderationsPipeline4-58 SPRU7334.4.2 Multicycle NOPsThe NOP instruction has an optional operand, count, that allows you to issuea singl

Performance Considerations4-59PipelineSPRU733Figure 4−30 shows how a multicycle NOP can be affected by a branch. If thedelay slots of a branch finish

Performance ConsiderationsPipeline4-60 SPRU7334.4.3 Memory ConsiderationsThe C67x DSP has a memory configuration with program memory in onephysical sp

Performance Considerations4-61PipelineSPRU733Depending on the type of memory and the time required to complete anaccess, the pipeline may stall to ens

Performance ConsiderationsPipeline4-62 SPRU7334.4.3.2 Memory Bank HitsMost C67x devices use an interleaved memory bank scheme, as shown inFigure 4−33.

Performance Considerations4-63PipelineSPRU733Table 4−41. Loads in Pipeline from Example 4−2i i + 1 i + 2 i + 3 i + 4 i + 5LDW .D1Bank 0E1 E2 E3 − E4 E

5-1InterruptsSPRU7339InterruptsThis chapter describes CPU interrupts, including reset and the nonmaskableinterrupt (NMI). It details the related CPU c

OverviewInterrupts5-2 SPRU7335.1 OverviewTypically, DSPs work in an environment that contains multiple externalasynchronous events. These events requi

Overview5-3InterruptsSPRU733Table 5−1. Interrupt PrioritiesPriority Interrupt Name Interrupt TypeHighest Reset ResetNMI NonmaskableINT4 MaskableINT5 M

OverviewInterrupts5-4 SPRU7335.1.1.2 Nonmaskable Interrupt (NMI)NMI is the second-highest priority interrupt and is generally used to alert theCPU of

Trademarksiv SPRU733Read This FirstTMS320C672x DSP Peripherals Overview Reference Guide (literaturenumber SPRU723) describes the peripherals availab

Control Register FileCPU Data Paths and Control2-14 SPRU733Table 2−7. Control Status Register (CSR) Field Descriptions Bit Field Value Description31−

Overview5-5InterruptsSPRU7335.1.1.4 Interrupt Acknowledgment (IACK) and Interrupt Number (INUMn)The IACK and INUMn signals alert hardware external to

OverviewInterrupts5-6 SPRU7335.1.2 Interrupt Service Table (IST)When the CPU begins processing an interrupt, it references the interruptservice table

Overview5-7InterruptsSPRU7335.1.2.1 Interrupt Service Fetch Packet (ISFP)An ISFP is a fetch packet used to service an interrupt. Figure 5−2 shows anIS

OverviewInterrupts5-8 SPRU733If the interrupt service routine for an interrupt is too large to fit in a single fetchpacket, a branch to the location o

Overview5-9InterruptsSPRU7335.1.2.2 Interrupt Service Table Pointer (ISTP)The reset fetch packet must be located at address 0, but the rest of the IST

OverviewInterrupts5-10 SPRU7335.1.3 Summary of Interrupt Control RegistersTable 5−2 lists the interrupt control registers on the C67x CPU.Table 5−2. I

Globally Enabling and Disabling Interrupts5-11InterruptsSPRU7335.2 Globally Enabling and Disabling Interrupts The control status register (CSR) contai

Globally Enabling and Disabling InterruptsInterrupts5-12 SPRU733Example 5−2. Code Sequence to Disable Maskable Interrupts GloballyMVC CSR,B0 ; get CSR

Individual Interrupt Control5-13InterruptsSPRU7335.3 Individual Interrupt ControlServicing interrupts effectively requires individual control of all t

Individual Interrupt ControlInterrupts5-14 SPRU7335.3.2 Status of InterruptsThe interrupt flag register (IFR) contains the status of INT4−INT15 and NM

Control Register File2-15CPU Data Paths and ControlSPRU733Table 2−7. Control Status Register (CSR) Field Descriptions (Continued)Bit DescriptionValueF

Individual Interrupt Control5-15InterruptsSPRU7335.3.4 Returning From Interrupt ServicingAfter RESET goes high, the control registers are brought to a

Interrupt Detection and ProcessingInterrupts5-16 SPRU7335.4 Interrupt Detection and ProcessingWhen an interrupt occurs, it sets a flag in the interrup

Interrupt Detection and Processing5-17InterruptsSPRU733Any pending interrupt will be taken as soon as pending branches arecompleted.Figure 5−4. Nonres

Interrupt Detection and ProcessingInterrupts5-18 SPRU7335.4.3 Actions Taken During Nonreset Interrupt ProcessingDuring CPU cycles 6 through 14 of Figu

Interrupt Detection and Processing5-19InterruptsSPRU7335.4.4 Setting the RESET Interrupt FlagRESET must be held low for a minimum of 10 clock cycles.

Interrupt Detection and ProcessingInterrupts5-20 SPRU7335.4.5 Actions Taken During RESET Interrupt ProcessingA low signal on the RESET pin is the only

Performance Considerations5-21InterruptsSPRU7335.5 Performance ConsiderationsThe interaction of the C6000 CPU and sources of interrupts present perfor

Programming ConsiderationsInterrupts5-22 SPRU7335.6 Programming ConsiderationsThe interaction of the C6000 CPUs and sources of interrupts present prog

Programming Considerations5-23InterruptsSPRU733Example 5−11. Code Using Single AssignmentLDW .D1 *A0,A6ADD .L1 A1,A2,A3NOP 3MPY .M1 A6,A4,A5 ; uses A6

Programming ConsiderationsInterrupts5-24 SPRU733Example 5−13 shows a C-based interrupt handler that allows nestedinterrupts. The steps are similar, al

Control Register FileCPU Data Paths and Control2-16 SPRU7332.7.5 Interrupt Clear Register (ICR)The interrupt clear register (ICR) allows you to manual

Programming Considerations5-25InterruptsSPRU733Example 5−13. C Interrupt Service Routine That Allows Nested Interrupts/* c6x.h contains declarations o

Programming ConsiderationsInterrupts5-26 SPRU7335.6.4 TrapsA trap behaves like an interrupt, but is created and controlled with software.The trap cond

A-1Instruction CompatibilitySPRU733Appendix AInstruction CompatibilityThe C62x, C64x, and C67x DSPs share an instruction set. All of the instruc-tions

Instruction CompatibilityInstruction CompatibilityA-2 SPRU733Table A−1. Instruction Compatibility Between C62x, C64x, C67x,and C67x+ DSPs (Continued)

Instruction CompatibilityA-3Instruction CompatibilitySPRU733Table A−1. Instruction Compatibility Between C62x, C64x, C67x,and C67x+ DSPs (Continued)I

Instruction CompatibilityInstruction CompatibilityA-4 SPRU733Table A−1. Instruction Compatibility Between C62x, C64x, C67x,and C67x+ DSPs (Continued)

Instruction CompatibilityA-5Instruction CompatibilitySPRU733Table A−1. Instruction Compatibility Between C62x, C64x, C67x,and C67x+ DSPs (Continued)I

Instruction CompatibilityInstruction CompatibilityA-6 SPRU733Table A−1. Instruction Compatibility Between C62x, C64x, C67x,and C67x+ DSPs (Continued)

B-1Mapping Between Instruction and Functional UnitSPRU733Appendix AMapping Between Instruction andFunctional UnitTable B−1 lists the instructions that

Mapping Between Instruction and Functional UnitMapping Between Instruction and Functional UnitB-2 SPRU733Table B−1. Functional Unit to Instruction Map

Control Register File2-17CPU Data Paths and ControlSPRU7332.7.6 Interrupt Enable Register (IER)The interrupt enable register (IER) enables and disable

Mapping Between Instruction and Functional UnitB-3Mapping Between Instruction and Functional UnitSPRU733Table B−1. Functional Unit to Instruction Mapp

Mapping Between Instruction and Functional UnitMapping Between Instruction and Functional UnitB-4 SPRU733Table B−1. Functional Unit to Instruction Map

Mapping Between Instruction and Functional UnitB-5Mapping Between Instruction and Functional UnitSPRU733Table B−1. Functional Unit to Instruction Mapp

Mapping Between Instruction and Functional UnitMapping Between Instruction and Functional UnitB-6 SPRU733Table B−1. Functional Unit to Instruction Map

C-1.D Unit Instructions and Opcode MapsSPRU733Appendix A.D Unit Instructions and Opcode MapsThis appendix lists the instructions that execute in the .

Instructions Executing in the .D Functional Unit.D Unit Instructions and Opcode MapsC-2 SPRU733C.1 Instructions Executing in the .D Functional UnitTab

Opcode Map Symbols and MeaningsC-3.D Unit Instructions and Opcode MapsSPRU733C.2 Opcode Map Symbols and MeaningsTable C−2 lists the symbols and meanin

Opcode Map Symbols and Meanings.D Unit Instructions and Opcode MapsC-4 SPRU733Table C−3. Address Generator Options for Load/Storemode Field Syntax Mod

32-Bit Opcode MapsC-5.D Unit Instructions and Opcode MapsSPRU733C.3 32-Bit Opcode MapsThe C67x CPU 32-bit opcodes used in the .D unit are mapped in Fi

D-1.L Unit Instructions and Opcode MapsSPRU733Appendix A.L Unit Instructions and Opcode MapsThis appendix lists the instructions that execute in the .

Control Register FileCPU Data Paths and Control2-18 SPRU7332.7.7 Interrupt Flag Register (IFR)The interrupt flag register (IFR) contains the status of

Instructions Executing in the .L Functional Unit.L Unit Instructions and Opcode MapsD-2 SPRU733D.1 Instructions Executing in the .L Functional UnitTab

Opcode Map Symbols and MeaningsD-3.L Unit Instructions and Opcode MapsSPRU733D.2 Opcode Map Symbols and MeaningsTable D−2 lists the symbols and meanin

32-Bit Opcode Maps.L Unit Instructions and Opcode MapsD-4 SPRU733D.3 32-Bit Opcode MapsThe C67x CPU 32-bit opcodes used in the .L unit are mapped in F

E-1.M Unit Instructions and Opcode MapsSPRU733Appendix A.M Unit Instructions and Opcode MapsThis appendix lists the instructions that execute in the .

Instructions Executing in the .M Functional Unit.M Unit Instructions and Opcode MapsE-2 SPRU733E.1 Instructions Executing in the .M Functional UnitTab

Opcode Map Symbols and MeaningsE-3.M Unit Instructions and Opcode MapsSPRU733E.2 Opcode Map Symbols and MeaningsTable E−2 lists the symbols and meanin

32-Bit Opcode Maps.M Unit Instructions and Opcode MapsE-4 SPRU733E.3 32-Bit Opcode MapsThe C67x CPU 32-bit opcodes used in the .M unit are mapped in F

F-1.S Unit Instructions and Opcode MapsSPRU733Appendix A.S Unit Instructions and Opcode MapsThis appendix lists the instructions that execute in the .

Instructions Executing in the .S Functional Unit.S Unit Instructions and Opcode MapsF-2 SPRU733F.1 Instructions Executing in the .S Functional UnitTab

Opcode Map Symbols and MeaningsF-3.S Unit Instructions and Opcode MapsSPRU733F.2 Opcode Map Symbols and MeaningsTable F−2 lists the symbols and meanin

Control Register File2-19CPU Data Paths and ControlSPRU7332.7.8 Interrupt Return Pointer Register (IRP)The interrupt return pointer register (IRP) con

32-Bit Opcode Maps.S Unit Instructions and Opcode MapsF-4 SPRU733F.3 32-Bit Opcode MapsThe C67x CPU 32-bit opcodes used in the .S unit are mapped in F

32-Bit Opcode MapsF-5.S Unit Instructions and Opcode MapsSPRU733Figure F−6. Call Unconditional, Immediate with Implied NOP 5 Instruction Format31 29 2

G-1No Unit Specified Instructions and Opcode MapsSPRU733Appendix ANo Unit Specified Instructions and Opcode MapsThis appendix lists the instructions t

Instructions Executing With No Unit SpecifiedNo Unit Specified Instructions and Opcode MapsG-2 SPRU733G.1 Instructions Executing With No Unit Specifie

32-Bit Opcode MapsG-3No Unit Specified Instructions and Opcode MapsSPRU733G.3 32-Bit Opcode MapsThe C67x CPU 32-bit opcodes used in the no unit instru

IndexIndex-1SPRU733Index1X and 2X paths 2-62-cycle DP instructions, .S-unit instructionconstraints 4-364-cycle instructions.L-unit instruction constra

IndexIndex-2 SPRU733BB instructionusing a displacement 3-69using a register 3-71B IRP instruction 3-73B NRP instruction 3-75B4 MODE bits 2-10B5 MODE

IndexIndex-3SPRU733compare for equalityfloating-pointdouble-precision values (CMPEQDP) 3-82single-precision values (CMPEQSP) 3-84signed integers (CMPE

IndexIndex-4 SPRU733cross paths 2-6CSR 2-13DDA1 and DA2 2-7data address paths 2-7DC pipeline phase 4-3DCC bits 2-13decoding instructions 4-3delay sl

IndexIndex-5SPRU733IEn bit 2-17IER 2-17IFn bit 2-18IFR 2-18INEX bitin FADCR 2-24in FAUCR 2-27in FMCR 2-31INFO bitin FADCR 2-24in FAUCR 2-27in FMCR 2-3

Control Register FileCPU Data Paths and Control2-20 SPRU7332.7.9 Interrupt Set Register (ISR)The interrupt set register (ISR) allows you to manually s

IndexIndex-6 SPRU733INTSPU instruction 3-122INVAL bitin FADCR 2-24in FAUCR 2-27in FMCR 2-31IRP 2-19ISn bit 2-20ISR 2-20ISTB bits 2-21ISTP 2-21Llaten

IndexIndex-7SPRU733move16-bit constant into upper bits of register(MVKH and MVKLH) 3-185between control file and register file(MVC) 3-180from register

IndexIndex-8 SPRU733multiply (continued)unsigned by unsignedunsigned 16 LSB by unsigned 16 LSB(MPYU) 3-174unsigned 16 LSB by unsigned 16 MSB(MPYLHU)

IndexIndex-9SPRU733PGIE bit 2-13pipelinedecode stage 4-3execute stage 4-5execution 4-12factors that provide programming flexibility 4-1fetch stage 4-2

IndexIndex-10 SPRU733returning from interrupt servicing 5-15REVISION ID bits 2-13RMODE bitsin FADCR 2-24in FMCR 2-31RSQRDP instruction 3-201RSQRSP i

IndexIndex-11SPRU733SUBC instruction 3-258SUBDP instruction 3-260.L-unit instruction constraints 4-51.S-unit instruction constraints 4-38pipeline oper

Control Register File2-21CPU Data Paths and ControlSPRU7332.7.10 Interrupt Service Table Pointer Register (ISTP)The interrupt service table pointer re

Control Register FileCPU Data Paths and Control2-22 SPRU7332.7.11 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)The NMI return pointer regi

Control Register File Extensions2-23CPU Data Paths and ControlSPRU7332.8 Control Register File ExtensionsThe C67x DSP has three additional configurati

ContentsvContentsSPRU733Contents1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Control Register File ExtensionsCPU Data Paths and Control2-24 SPRU733Figure 2−14. Floating-Point Adder Configuration Register (FADCR)31 27 26 25 24 2

Control Register File Extensions2-25CPU Data Paths and ControlSPRU733Table 2−14. Floating-Point Adder Configuration Register (FADCR)Field Descriptions

Control Register File ExtensionsCPU Data Paths and Control2-26 SPRU733Table 2−14. Floating-Point Adder Configuration Register (FADCR)Field Description

Control Register File Extensions2-27CPU Data Paths and ControlSPRU7332.8.2 Floating-Point Auxiliary Configuration Register (FAUCR)The floating-point a

Control Register File ExtensionsCPU Data Paths and Control2-28 SPRU733Table 2−15. Floating-Point Auxiliary Configuration Register (FAUCR)Field Descrip

Control Register File Extensions2-29CPU Data Paths and ControlSPRU733Table 2−15. Floating-Point Auxiliary Configuration Register (FAUCR)Field Descript

Control Register File ExtensionsCPU Data Paths and Control2-30 SPRU733Table 2−15. Floating-Point Auxiliary Configuration Register (FAUCR)Field Descrip

Control Register File Extensions2-31CPU Data Paths and ControlSPRU7332.8.3 Floating-Point Multiplier Configuration Register (FMCR)The floating-point m

Control Register File ExtensionsCPU Data Paths and Control2-32 SPRU733Table 2−16. Floating-Point Multiplier Configuration Register (FMCR)Field Descrip

Control Register File Extensions2-33CPU Data Paths and ControlSPRU733Table 2−16. Floating-Point Multiplier Configuration Register (FMCR)Field Descript

Contentsvi SPRU733Contents3 Instruction Set 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Control Register File ExtensionsCPU Data Paths and Control2-34 SPRU733Table 2−16. Floating-Point Multiplier Configuration Register (FMCR)Field Descrip

3-1Instruction SetSPRU733Instruction SetThis chapter describes the assembly language instructions of theTMS320C67x DSP. Also described are parallel op

Instruction Operation and Execution NotationsInstruction Set3-2 SPRU7333.1 Instruction Operation and Execution NotationsTable 3−1 explains the symbols

Instruction Operation and Execution Notations3-3Instruction SetSPRU733Table 3−1. Instruction Operation and Execution Notations (Continued)Symbol Mean

Instruction Operation and Execution NotationsInstruction Set3-4 SPRU733Table 3−1. Instruction Operation and Execution Notations (Continued)Symbol Mea

Instruction Operation and Execution Notations3-5Instruction SetSPRU733Table 3−1. Instruction Operation and Execution Notations (Continued)Symbol Mean

Instruction Operation and Execution NotationsInstruction Set3-6 SPRU733Table 3−1. Instruction Operation and Execution Notations (Continued)Symbol Mea

Instruction Syntax and Opcode Notations3-7Instruction SetSPRU7333.2 Instruction Syntax and Opcode NotationsTable 3−2 explains the syntaxes and opcode

Instruction Syntax and Opcode NotationsInstruction Set3-8 SPRU733Table 3−2. Instruction Syntax and Opcode Notations (Continued)Symbol Meaningscstnbit

Overview of IEEE Standard Single- and Double-Precision Formats3-9Instruction SetSPRU7333.3 Overview of IEEE Standard Single- and Double-Precision Form

ContentsviiContentsSPRU733CLR (Clear a Bit Field) 3-77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Overview of IEEE Standard Single- and Double-Precision FormatsInstruction Set3-10 SPRU733Table 3−3. IEEE Floating-Point NotationsSymbol Meanings Sign

Overview of IEEE Standard Single- and Double-Precision Formats3-11Instruction SetSPRU733Figure 3−1 shows the fields of a single-precision floating-poi

Overview of IEEE Standard Single- and Double-Precision FormatsInstruction Set3-12 SPRU733Table 3−5 shows hexadecimal and decimal values for some singl

Overview of IEEE Standard Single- and Double-Precision Formats3-13Instruction SetSPRU733Normalized:−1s × 2(e−1023) × 1.f 0 < e < 2047Denorma

Delay SlotsInstruction Set3-14 SPRU7333.4 Delay SlotsThe execution of floating-point instructions can be defined in terms of delayslots and functional

Delay Slots3-15Instruction SetSPRU733Table 3−8. Delay Slot and Functional Unit LatencyInstruction TypeDelaySlotsFunctionalUnit LatencyRead Cycles†Writ

Parallel OperationsInstruction Set3-16 SPRU7333.5 Parallel OperationsInstructions are always fetched eight at a time. This constitutes a fetch packet.

Parallel Operations3-17Instruction SetSPRU733Example 3−1. Fully Serial p-Bit Pattern in a Fetch PacketThis p-bit pattern:00000000InstructionAInstructi

Parallel OperationsInstruction Set3-18 SPRU733Example 3−3. Partially Serial p-Bit Pattern in a Fetch PacketThis p-bit pattern:31 0 31 0 31 0 31 000113

Conditional Operations3-19Instruction SetSPRU7333.6 Conditional OperationsMost instructions can be conditional. The condition is controlled by a 3-bit

Contentsviii SPRU733ContentsMPYI (Multiply 32-Bit by 32-Bit Into 32-Bit Result) 3-157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPYID

Resource ConstraintsInstruction Set3-20 SPRU7333.7 Resource ConstraintsNo two instructions within the same execute packet can use the sameresources. A

Resource Constraints3-21Instruction SetSPRU7333.7.3 Constraints on Cross Paths (1X and 2X)One unit (either a .S, .L, or .M unit) per data path, per ex

Resource ConstraintsInstruction Set3-22 SPRU7333.7.4 Constraints on Loads and StoresLoad and store instructions can use an address pointer from one re

Resource Constraints3-23Instruction SetSPRU7333.7.5 Constraints on Long (40-Bit) DataBecause the .S and .L units share a read register port for long s

Resource ConstraintsInstruction Set3-24 SPRU7333.7.6 Constraints on Register ReadsMore than four reads of the same register cannot occur on the same c

Resource Constraints3-25Instruction SetSPRU7333.7.7 Constraints on Register WritesTwo instructions cannot write to the same register on the same cycle

Resource ConstraintsInstruction Set3-26 SPRU7333.7.8 Constraints on Floating-Point InstructionsIf an instruction has a multicycle functional unit late

Resource Constraints3-27Instruction SetSPRU733MPYDP No other instruction on the same side can use the crosspath on cycles i, i + 1, i + 2, and i + 3.M

Resource ConstraintsInstruction Set3-28 SPRU733MPYI A 4-cycle instruction cannot be scheduled on that func-tional unit on cycle i + 4, i + 5, or i + 6

Resource Constraints3-29Instruction SetSPRU733MPYSPDP A 4-cycle instruction cannot be scheduled on that func-tional unit on cycle i + 2 or i + 3.A MPY

ContentsixContentsSPRU733SPINT (Convert Single-Precision Floating-Point Value to Integer) 3-228. . . . . . . . . . . . . . . SPTRUNC (Convert Single-P

Addressing ModesInstruction Set3-30 SPRU7333.8 Addressing ModesThe addressing modes on the C67x DSP are linear, circular using BK0, andcircular using

Addressing Modes3-31Instruction SetSPRU7333.8.2 Circular Addressing ModeThe BK0 and BK1 fields in AMR specify the block sizes for circular addressing,

Addressing ModesInstruction Set3-32 SPRU7333.8.2.2 ADDA and SUBA Instructions As with linear address arithmetic, offsetR/cst is shifted left by 3, 2,

Addressing Modes3-33Instruction SetSPRU733Table 3−10. Indirect Address Generation for Load/StoreAddressing TypeNo Modification of Address RegisterPrei

Instruction CompatibilityInstruction Set3-34 SPRU7333.9 Instruction CompatibilityThe C62x, C64x, and C67x DSPs share an instruction set. All of the in

The way each instruction is described Example3-35 Instruction SetSPRU733The way each instruction is described.ExampleSyntax EXAMPLE (.unit) src, dst.

Example The way each instruction is described3-36 Instruction Set SPRU733Table 3−12. Relationships Between Operands, Operand Size, Signed/Unsigned,F

The way each instruction is described Example3-37 Instruction SetSPRU733Compatibility The C62x, C64x, and C67x DSPs share an instruction set. All of

ABS Absolute Value With Saturation3-38 Instruction Set SPRU733Absolute Value With SaturationABSSyntax ABS (.unit) src2, dst.unit = .L1 or .L2Compati

Absolute Value With Saturation ABS3-39 Instruction SetSPRU733Instruction Type Single-cycleDelay Slots 0See Also ABSDP, ABSSPExample 1ABS .L1 A1,A5Bef