Texas Instruments TMS320 DSP manuály

Uživatelské manuály a uživatelské příručky pro Dekodéry Texas Instruments TMS320 DSP.
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Texas instruments TMS320 DSP Uživatelský manuál (88 strany)

Značka: Texas-instruments | Kategorie: Dekodéry | Velikost: 0.59 MB |

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Tabulka s obsahem

User's Guide

1

Submit Documentation Feedback

2

Contents

3

Read This First

7

Related Documentation

8

Text Conventions

8

Overview

9

1.1 Scope of the Standard

10

1.1.1 Rules and Guidelines

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1.3 Goals of the Standard

12

1.4 Intentional Omissions

12

1.5 System Architecture

13

1.5.1 Frameworks

13

1.5.2 Algorithms

14

1.5.3 Core Run-Time Support

14

Chapter 2

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2.1 Use of C Language

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2.2 Threads and Reentrancy

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2.2.1 Threads

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2.2.3 Reentrancy

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2.2.4 Example

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2.3 Data Memory

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2.3.1 Memory Spaces

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Data Memory

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2.4 Program Memory

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2.5 ROM-ability

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2.6 Use of Peripherals

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Algorithm Component Model

25

3.1 Interfaces and Modules

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3.1.1 External Identifiers

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3.1.2 Naming Conventions

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3.1.4 Module Instance Objects

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Interfaces and Modules

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3.1.7 Module Configuration

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3.1.8 Example Module

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3.1.10 Interface Inheritance

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3.1.11 Summary

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3.2 Algorithms

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3.3 Packaging

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3.3.1 Object Code

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3.3.2 Header Files

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3.3.3 Debug Verses Release

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Packaging

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Chapter 4

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4.1 Data Memory

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4.1.1 Heap Memory

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4.1.2 Stack Memory

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4.2 Program Memory

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4.3 Interrupt Latency

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4.4 Execution Time

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4.4.1 MIPS Is Not Enough

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4.4.2 Execution Time Model

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Execution Time

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DSP-Specific Guidelines

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5.1 CPU Register Types

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5.2 Use of Floating Point

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5.3.1 Endian Byte Ordering

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5.3.2 Data Models

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5.3.3 Program Model

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5.3.4 Register Conventions

48

5.3.5 Status Register

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5.3.6 Interrupt Latency

49

5.4.1 Data Models

49

5.4.2 Program Models

49

5.4.3 Register Conventions

51

5.4.4 Status Registers

51

5.4.5 Interrupt Latency

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5.5.1 Stack Architecture

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5.5.2 Data Models

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5.5.3 Program Models

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5.5.4 Relocatability

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5.5.5 Register Conventions

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5.5.6 Status Bits

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5.6 TMS320C24xx Guidelines

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5.6.1 General

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5.6.2 Data Models

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5.6.3 Program Models

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5.6.4 Register Conventions

57

5.6.5 Status Registers

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5.6.6 Interrupt Latency

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5.7.1 Data Models

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5.7.2 Program Models

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5.7.3 Register Conventions

59

5.7.4 Status Registers

59

5.7.5 Interrupt Latency

60

Use of the DMA Resource

61

6.1 Overview

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6.2 Algorithm and Framework

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6.4 Logical Channel

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6.5 Data Transfer Properties

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6.7 Abstract Interface

65

6.8 Resource Characterization

66

6.9 Runtime APIs

67

6.15.1 Non-Preemptive System

71

6.15.3 Preemptive System

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Rules and Guidelines

75

A.1 General Rules

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A.3 DMA Rules

77

A.4 General Guidelines

78

A.5 DMA Guidelines

79

Core Run-Time APIs

81

Bibliography

83

Glossary

85

Glossary of Terms

86

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