Texas Instruments TMS320DM355 Uživatelský manuál stáhnout pdf

www.ti.com

PRODUCT PREVIEW

1 TMS320DM355 Digital Media System-on-Chip (DMSoC)

1.1 Features

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

encoder

• High-Performance Digital Media

System-on-Chip • External Memory Interfaces (EMIFs)

– 216- and 270-MHz ARM926EJ-S Clock Rate – DDR2 and mDDR SDRAM 16-bit wide EMIF

With 256 MByte Address Space (1.8-V I/O)

– Fully Software-Compatible With ARM9

– Asynchronous16-/8-bit Wide EMIF (AEMIF)

• ARM926EJ-S Core

• Flash Memory Interfaces

– Support for 32-Bit and 16-Bit (Thumb Mode)

– NAND (8-/16-bit Wide Data)

Instruction Sets

– OneNAND(16-bit Wide Data)

– DSP Instruction Extensions and Single

Cycle MAC

• Flash Card Interfaces

– ARM Jazelle Technology

– Two Multimedia Card (MMC) / Secure

– EmbeddedICE-RT Logic for Real-Time Digital (SD/SDIO)

Debug

– SmartMedia

• ARM9 Memory Architecture

• Enhanced Direct-Memory-Access (EDMA)

– 16K-Byte Instruction Cache Controller (64 Independent Channels)

– 8K-Byte Data Cache

• USB Port with Integrated 2.0 High-Speed PHY

that Supports

– 32K-Byte RAM

– USB 2.0 Full and High-Speed Device

– 8K-Byte ROM

– USB 2.0 Low, Full, and High-Speed Host

– Little Endian

• Three 64-Bit General-Purpose Timers (each

• Video Processing Subsystem

configurable as two 32-bit timers)

– Front End Provides:

• One 64-Bit Watch Dog Timer

• Hardware IPIPE for Real-Time Image

Processing • Three UARTs (One fast UART with RTS and

CTS Flow Control)

• CCD and CMOS Imager Interface

• Three Serial Port Interfaces (SPI) each with

• 14-Bit Parallel AFE (Analog Front End)

two Chip-Selects

Interface Up to 67.5 MHz

• One Master/Slave Inter-Integrated Circuit

• Glueless Interface to Common Video

C) Bus™

Decoders

• BT.601/BT.656 Digital YCbCr 4:2:2 • Two Audio Serial Port (ASP)

(8-/16-Bit) Interface

– I2S and TDM I2S

• Histogram Module

– AC97 Audio Codec Interface

• Resize Engine

– S/PDIF via Software

– Resize Images From 1/16x to 8x

– Standard Voice Codec Interface (AIC12)

– Separate Horizontal/Vertical Control

– SPI Protocol (Master Mode Only)

– Two Simultaneous Output Paths

• Four Pulse Width Modulator (PWM) Outputs

– Back End Provides:

• Four RTO (Real Time Out) Outputs

• Hardware On-Screen Display (OSD)

• Up to 104 General-Purpose I/O (GPIO) Pins

• Composite NTSC/PAL video encoder

(Multiplexed with Other Device Functions)

output

• On-Chip ARM ROM Bootloader (RBL) to Boot

• 8-/16-bit YCC and Up to 18-Bit RGB666

From NAND Flash, MMC/SD, or UART

Digital Output

• Configurable Power-Saving Modes

• BT.601/BT.656 Digital YCbCr 4:2:2

• Crystal or External Clock Input (typically

(8-/16-Bit) Interface

24 MHz or 36 MHz)

• Supports digital HDTV (720p/1080i)

• Flexible PLL Clock Generators

output for connection to external

• Debug Interface Support

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

C-bus is a trademark of Texas Instruments.

Windows is a trademark of Microsoft.

All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

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Shrnutí obsahu

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www.ti.comPRODUCT PREVIEW1 TMS320DM355 Digital Media System-on-Chip (DMSoC)1.1 FeaturesTMS320DM355Digital Media System-on-Chip (DMSoC)SPRS463A – SEPTE

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www.ti.comPRODUCT PREVIEW5.5.2 MXI2 (27-MHz) Oscillator (optional oscillator)Crystal27MHzC1 C2MXI2MXO2 VSS_MX2L1VDDA_PLL2VSSA_PLL20.1 F1 FCLC1C2(C1C2

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www.ti.comPRODUCT PREVIEW5.5.3 Clock PLL Electrical Data/Timing (Input and Output Clocks)MXI/CLKIN234451MXI/CLKIN234451TMS320DM355Digital Media System

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www.ti.comPRODUCT PREVIEWEM_CE[1:0]EM_BA[1:0]1312EM_A[13:0]EM_OEEM_D[15:0]EM_WE1059748631EM_CE[1:0]EM_BA[1:0]EM_A[13:0]EM_WEEM_D[15:0]EM_OE15116182022

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www.ti.comPRODUCT PREVIEWCVDD19W18DDR_GATE017DDR_DQ1516DDR_DQ1315DDR_DQ1114DDR_DQ1013DDR_DQ0712DDR_DQ0511DDR_DQ0110DDR_WEEM_A13VVSSDDR_GATE1DDR_DQ14DD

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www.ti.comPRODUCT PREVIEW34333536373031Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+nDa+n+1EM_CLKEM_CE[1:0]EM_ADVEM_BA0,EM_A[13:0],EM_BA1EM_D[15:0]EM_OEEM_WAIT3839T

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www.ti.comPRODUCT PREVIEWPCLK(Positive Edge Clocking)PCLK(Negative Edge Clocking)7,9HD/VDCI[7:0]/YI[7:0]/CCD[13:0]8,1011,1312,1456C_WE/C_FIELDPCLK

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www.ti.comPRODUCT PREVIEWDIN<9:0>MSBLSBDACDigitalInputExampleforExternalCircuitIout[mA]1.4mA0DACOutputCurrentCBG0.1 FmVREFVideoDACRBI

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IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,improvemen

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