Texas-instruments TMS320C642x DSP Uživatelský manuál

TMS320C642x DSPPhase-Locked Loop Controller (PLLC)User's GuideLiterature Number: SPRUES0BDecember 2007

www.ti.com1.2.4 I/O DomainsDevice ClockingThe I/O domains refer to the frequencies of the peripherals that communicate through device pins. Inmany cas

www.ti.com2 PLL Controller2.1 PLL ModulePLL ControllerThe C642x DSP has two PLLs (PLL1 and PLL2) that provide clocks to different parts of the system.

www.ti.com2.2 PLL1 ControlPLLDIV1(/1)PLLDIV3(/6)PLLDIV2(/3)SYSCLK1(CLKDIV1Domain)SYSCLK3(CLKDIV6Domain)SYSCLK2(CLKDIV3Domain)10PLLMPLL01CLKMODEC

www.ti.com2.2.1 Device Clock Generation2.2.2 Steps for Changing PLL1/Core Domain Frequency2.2.2.1 Initialization to PLL Mode from PLL Power DownPLL Co

www.ti.com2.2.2.2 Changing PLL MultiplierPLL Controller9. If necessary, program PLLDIV1, PLLDIV2, and PLLDIV3 registers to change the SYSCLK1, SYSCLK2

www.ti.com2.2.2.3 Changing SYSCLK DividersPLL ControllerThis section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider

www.ti.com2.3 PLL2 ControlPLLDIV1 (/2)10PLLMPLL01BPDIVCLKMODECLKINOSCINPLLENPLL2_SYSCLK1(DDR2 PHY)PLL2_SYSCLKBP(DDR2 VTP)PLLOUTPLL ControllerPLL2 prov

www.ti.com2.3.1 Device Clock Generation2.3.2 Steps for Changing PLL2 Frequency2.3.2.1 DDR2 Considerations When Modifying PLL2 FrequencyPLL ControllerP

www.ti.com2.3.2.2 Initialization to PLL Mode from PLL Power DownPLL ControllerExample 2. PLL2 Frequency Change Steps When DDR2 Memory Controller is In

www.ti.com2.3.2.3 Changing PLL MultiplierPLL Controller8. Program the required multiplier value in PLLM.9. If necessary, program PLLDIV1 register to c

2 SPRUES0B – December 2007Submit Documentation Feedback

www.ti.com2.3.2.4 Changing SYSCLK DividersPLL ControllerThis section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider

www.ti.com2.4 PLL Controller RegistersPLL ControllerTable 8 lists the base address and end address for the PLL controllers. Table 9 lists the memory-m

www.ti.com2.4.1 Peripheral ID Register (PID)2.4.2 Reset Type Status Register (RSTYPE)PLL ControllerThe peripheral ID register (PID) is shown in Figure

www.ti.com2.4.3 PLL Control Register (PLLCTL)PLL ControllerThe PLL control register (PLLCTL) is shown in Figure 6 and described in Table 12 .Figure 6.

www.ti.com2.4.4 PLL Multiplier Control Register (PLLM)2.4.5 PLL Controller Divider 1 Register (PLLDIV1)PLL ControllerThe PLL multiplier control regist

www.ti.com2.4.6 PLL Controller Divider 2 Register (PLLDIV2)2.4.7 PLL Controller Divider 3 Register (PLLDIV3)PLL ControllerThe PLL controller divider 2

www.ti.com2.4.8 Oscillator Divider 1 Register (OSCDIV1)PLL ControllerThe oscillator divider 1 register (OSCDIV1) is shown in Figure 11 and described i

www.ti.com2.4.9 Bypass Divider Register (BPDIV)PLL ControllerThe bypass divider register (BPDIV) is shown in Figure 12 and described in Table 18 . Byp

www.ti.com2.4.10 PLL Controller Command Register (PLLCMD)2.4.11 PLL Controller Status Register (PLLSTAT)PLL ControllerThe PLL controller command regis

www.ti.com2.4.12 PLL Controller Clock Align Control Register (ALNCTL)PLL ControllerThe PLL controller clock align control register (ALNCTL) is shown i

ContentsPreface ... 51 Dev

www.ti.com2.4.13 PLLDIV Ratio Change Status Register (DCHANGE)PLL ControllerThe PLLDIV ratio change status register (DCHANGE) is shown in Figure 16 an

www.ti.com2.4.14 Clock Enable Control Register (CKEN)PLL ControllerThe clock enable control register (CKEN) is shown in Figure 17 and described in Tab

www.ti.com2.4.15 Clock Status Register (CKSTAT)PLL ControllerThe clock status register (CKSTAT) is shown in Figure 18 and described in Table 24 . CKST

www.ti.com2.4.16 SYSCLK Status Register (SYSTAT)PLL ControllerThe SYSCLK status register (SYSTAT) is shown in Figure 19 and described in Table 25 . In

www.ti.comAppendix A Revision HistoryAppendix ATable A-1 lists the changes made since the previous version of this document.Table A-1. Document Revisi

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,improvemen

List of Figures1 Overall Clocking Diagram ... 72 PLL1

PrefaceSPRUES0B – December 2007Read This FirstAbout This ManualDescribes the operation of the phase-locked loop controller (PLLC) in the TMS320C642x D

1 Device Clocking1.1 Overview1.2 Clock Domains1.2.1 Core DomainsUser's GuideSPRUES0B – December 2007Phase-Locked Loop Controller (PLLC)The C642x

www.ti.comDSP SubsystemSYSCLK1SYSCLK3SCREDMADDR2 PHYDDR2 VTPDDR2 Mem CtlrPLLDIV1 (/2)BPDIVPLL Controller 2PLL Controller 1PLLDIV2 (/3)PLLDIV3 (/6)PLLD

www.ti.com1.2.2 Core Frequency FlexibilityDevice ClockingThe core frequency domain clocks are supplied by the PLL controller 1 (PLLC1). These domain c

www.ti.com1.2.3 DDR2/EMIF ClockDevice ClockingThe DDR2 interface has a dedicated clock driven from PLL2. This is a separate clock system from thePLL1