Texas-instruments TMS320DM646X DMSOC Uživatelský manuál Strana 25
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Hodnocené. / 5. Na základě hodnocení zákazníků
Bit 7
Bit 7
Bit 7
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 6
Bit 5 Bit 4 Bit 2Bit 3 Bit 1 Bit 0
Bit 6
Bit 6
Bit 1Bit 3 Bit 2Bit 4Bit 5
Bit 5 Bit 4 Bit 2Bit 3 Bit 1
Bit 0
Bit 0
p8o
p8o
p8e
p8e
p16e
p16o
p32e
Byte 1
Byte 2
Byte 3
Byte 4
Bit 6
Bit 6
Bit 6
Bit 6
Byte 2 Bit 7
Byte 4
Byte 3
Bit 7
Bit 7
Byte 1 Bit 7
Bit 1Bit 3 Bit 2Bit 4Bit 5
Bit 5
Bit 5 Bit 4
Bit 4 Bit 2
Bit 2Bit 3
Bit 3
Bit 1
Bit 1
Bit 5 Bit 4 Bit 2Bit 3 Bit 1
p16e
p8o
Bit 0
p16o
Bit 0
Bit 0
p8o
p8e
p32o
Bit 0
p8e
p2048e
p2048o
p1o p1e p1ep1o p1ep1o p1o p1e
p2o p2e p2o p2e
p4o p4e
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Architecture
2.5.6.6 ECC Generation
If the CSnNAND bit in the NAND Flash control register (NANDFCR) is set to 1, the EMIF supports ECC
calculation for up to 512 bytes for the corresponding chip select care. To perform the ECC calculation, the
CS2ECC bit in NANDFCR must be set to 1. The ECC calculation for each chip select space is
independent of each other. It is the responsibility of the software to start the ECC calculation by writing to
the CS2ECC bit prior to issuing a write or read to NAND Flash. It is also the responsibility of the software
to read the calculated ECC from the NAND Flash 1 ECC register (NANDF1ECC) once the transfer to
NAND Flash has completed. If the software writes or reads more than 512 bytes, the ECC will be
incorrect. There is a NANDECCn for each chip select space and when read, the corresponding CSnECC
bit in NANDFCR is cleared. The NANDF1ECC is cleared upon writing a 1 to the CS2ECC bit. Figure 9
shows the algorithm used to calculate the ECC value for an 8-bit NAND Flash.
For an 8-bit NAND Flash p1e through p4e are column parities and p8e through p2048 are row parities.
Similarly, the algorithm can be extended to a 16-bit NAND Flash. For a 16-bit NAND Flash p1e through
p8e are column parities and p16e through p2048 are row parities. The software must ignore the unwanted
parity bits if ECC is desired for less than 512 bytes of data. For example. p2048e and p2048o are not
required for ECC on 256 bytes of data. Similarly, p1024e, p1024o, p2048e, and p2048o are not required
for ECC on 128 bytes of data.
Figure 9. ECC Value for 8-Bit NAND Flash
25
SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF)
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Copyright © 2010, Texas Instruments Incorporated
- User's Guide 1
- SPRUEQ7C–February 2010 2
- Read This First 6
- 1.3 Functional Block Diagram 9
- 2 Architecture 9
- 2.1 Clock Control 9
- 2.2 EMIF Requests 9
- 2.3 Signal Descriptions 10
- 2.4 Pin Multiplexing 10
- Submit Documentation Feedback 11
- Architecture 12
- 3 Use Cases 30
- Use Cases 31
- 3.2 Interfacing to NAND Flash 39
- 4 Registers 48
- Registers 49
- Appendix A Revision History 63
- IMPORTANT NOTICE 64
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