Texas Instruments TMS320C2802 Uživatelský manuál

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
Digital Signal Processors
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS230L
October 2003Revised December 2009
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Strany 1 - Data Manual

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015Digital Signal ProcessorsData ManualP

Strany 2 - Contents

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 3 - Contents 3

0.050.0100.0150.0200.0250.010 20 30 40 50 60 70 80 90 100SYSCLKOUT (MHz)Current (mA)IDD IDDA18 IDDIO IDD3VFL 3.3-V current1.8-V current0.0100.0200.03

Strany 4

Current Vs SYSCLKOUT02040608010012014016018020010 20 30 40 50 60 70 80 90 10SYSCLKOUT (MHz)Current (mA)IDD IDDA18 1.8v current IDDIO IDD3VFL 3.3v curr

Strany 5 - List of Figures

EMU0EMU1TRSTTMSTDITDOTCKVDDIODSPEMU0EMU1TRSTTMSTDITDOTCKTCK_RET131421371196inchesorlessPDGNDGNDGNDGNDGND54681012JTAGHeaderVDDIOTMS320F2809, TMS320

Strany 6

Transmission Line4.0 pF 1.85 pFZ0 = 50 Ω(Α)Tester Pin ElectronicsData Sheet Timing Reference PointOutputUnderTest42 Ω 3.5 nHDevice Pin(B)TMS320F2809,

Strany 7 - List of Tables

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 8

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 9 - Digital Signal Processors

C4C3XCLKOUT(B)XCLKIN(A)C5C9C10C1C8C6TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015S

Strany 10 - 1.2 Getting Started

tw(RSL1)th(boot-mode)(B)VDDIO, VDD3VFLVDDA2, VDDAIO(3.3 V)XCLKINX1/X2XRSBoot-ModePinsVDD, VDD1A18,VDD2A18(1.8 V)XCLKOUTI/O Pins(C)User-Code DependentU

Strany 11 - 2 Introduction

th(boot-mode)(A)tw(RSL2)XCLKINX1/X2XRSBoot-ModePinsXCLKOUTI/O PinsAddress/Data/Control(Internal)Boot-ROM Execution StartsUser-Code Execution StartsUse

Strany 12

OSCCLKSYSCLKOUTWrite to PLLCROSCCLK * 2(Current CPUFrequency)OSCCLK/2(CPU Frequency While PLL is StabilizingWith the Desired Frequency. This Period(PL

Strany 13

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 14 - 2.1 Pin Assignments

GPIO Signal1Sampling WindowOutput FromQualifier1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0SYSCLKOUTQUALPRD = 1(SYSCLKOUT/2)(SYSCLKOUT cycle * 2 * QUALPR

Strany 15 - Introduction 15

GPIOxnXCLKOUTtw(GPI)TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230

Strany 16

WAKE INT(A)XCLKOUTAddress/Data(internal)td(WAKE−IDLE)tw(WAKE−INT)TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801

Strany 17 - Introduction 17

tw(WAKE-INT)td(WAKE-STBY)td(IDLE−XCOL)Wake−upSignalX1/X2 orX1 or XCLKINXCLKOUTSTANDBY Normal ExecutionSTANDBYFlushing Pipeline(A)(B)(C)(D)(E)(F)Device

Strany 18

td(IDLE−XCOL)X1/X2 or XCLKINXCLKOUTHALT HALTWake-up LatencyFlushing Pipelinetd(WAKE−HALT)(A)(B)(C)(D)DeviceStatus(E)(G)(F)PLL Lock-up TimeNormalExecut

Strany 19 - 2.2 Signal Descriptions

PWM(B)TZXCLKOUT(A)tw(TZ)td(TZ-PWM)HZTMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015w

Strany 20

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 21

ADCSOCAO orADCSOCBOtw(ADCSOCAL)XNMI, XINT1, XINT2tw(INT)Interrupt Vectortd(INT)Address bus (internal)TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802,

Strany 22

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 23

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 24 - See Table 2-2 for details

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 25 - 3 Functional Overview

94SPISOMISPISIMOSPICLK (clock polarity = 1)SPICLK (clock polarity = 0)Master In DataMust Be ValidMaster Out Data Is Valid85321SPISTE(A)TMS320F2809, TM

Strany 26 - 3.1 Memory Maps

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 27 - Figure 3-3. F2808 Memory Map

Data Valid11SPISOMISPISIMOSPICLK (clock polarity = 1)SPICLK (clock polarity = 0)Master In Data MustBe ValidMaster Out Data Is Valid1761032SPISTE(A)TMS

Strany 28 - Figure 3-4. F2806 Memory Map

2015SPISIMOSPISOMISPICLK(clock polarity = 1)SPICLK(clock polarity = 0)SPISIMO DataMust Be ValidSPISOMI Data Is Valid1916141312SPISTE(A)TMS320F2809, TM

Strany 29

Data Valid22SPISIMOSPISOMISPICLK(clock polarity = 1)SPICLK(clock polarity = 0)SPISIMO DataMust Be ValidSPISOMI Data Is Valid211218171413SPISTE(A)TMS32

Strany 30

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 31

ADC Power Up DelayADC Ready for ConversionsPWDNBGPWDNREFPWDNADCRequest forADCConversiontd(BGR)td(PWD)TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802,

Strany 32

acRsADCIN0Cp10 pFRon1 kΩ1.64 pFChSwitchTypical Values of the Input Circuit Components:Switch Resistance (Ron): 1 kΩSampling Capacitor (Ch): 1.64 pFPa

Strany 33 - Table 3-6. Wait-states

Analog Input onChannel Ax or BxADC ClockSample and HoldSH PulseSMODE Bittdschx_ntdschx_n+1Sample nSample n+1Sample n+2tSHADC Event Trigger fromePWM or

Strany 34 - 3.2.3 Peripheral Bus

Analog Input onChannel AxAnalog Input onChannel BxADC ClockSample and HoldSH PulsetSHtdschA0_ntdschB0_ntdschB0_n+1Sample nSample n+1Sample n+2tdschA0_

Strany 35 - 3.2.7 M0, M1 SARAMs

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 36 - 3.2.9 Boot ROM

N +(SINAD * 1.76)6.02TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER

Strany 37 - 3.2.10 Security

+ƪǒta(fp)tc(SCO)Ǔ* 1ƫ(round up to the next highest integer) or 0, whichever is larger(round up to the next highest integer) or 1, whichever is larger+

Strany 38

+ƪǒta(rp)tc(SCO)Ǔ* 1ƫ(round up to the next highest integer) or 0, whichever is larger+ƪǒta(rr)tc(SCO)Ǔ* 1ƫ(round up to the next highest integer) or 1,

Strany 39 - 3.2.20 Control Peripherals

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 40 - 3.3 Register Map

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 41

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 42 - 3.5 Interrupts

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 43 - Functional Overview 43

PACKAGE OPTION ADDENDUMwww.ti.com5-Nov-2010Addendum-Page 1PACKAGING INFORMATIONOrderable DeviceStatus (1)Package Type PackageDrawingPins Package QtyEc

Strany 44

PACKAGE OPTION ADDENDUMwww.ti.com5-Nov-2010Addendum-Page 2Orderable DeviceStatus (1)Package Type PackageDrawingPins Package QtyEco Plan (2)Lead/Ball F

Strany 45 - 3.5.1 External Interrupts

PACKAGE OPTION ADDENDUMwww.ti.com5-Nov-2010Addendum-Page 3Orderable DeviceStatus (1)Package Type PackageDrawingPins Package QtyEco Plan (2)Lead/Ball F

Strany 46 - 3.6 System Control

504948474645444342414039383736353433323130292827267677787980818283848586878889909192939495969798991007574737271706968676665646362616059585756555453525

Strany 47 - 3.6.1 OSC and PLL Block

PACKAGE OPTION ADDENDUMwww.ti.com5-Nov-2010Addendum-Page 4Orderable DeviceStatus (1)Package Type PackageDrawingPins Package QtyEco Plan (2)Lead/Ball F

Strany 48

MECHANICAL DATAMPBG028B FEBRUARY 1997 – REVISED MAY 20021POST OFFICE BOX 655303 • DALLAS, TEXAS 75265GGM (S–PBGA–N100) PLASTIC BALL GRID ARRAY 0,080,1

Strany 50

MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 19961POST OFFICE BOX 655303 • DALLAS, TEXAS 75265PZ (S-PQFP-G100) PLASTIC QUAD FLATP

Strany 51 - 3.6.2 Watchdog Block

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

Strany 52 - 3.7 Low-Power Modes Block

504948474645444342414039383736353433323130292827267677787980818283848586878889909192939495969798991007574737271706968676665646362616059585756555453525

Strany 53 - 4 Peripherals

504948474645444342414039383736353433323130292827267677787980818283848586878889909192939495969798991007574737271706968676665646362616059585756555453525

Strany 54

504948474645444342414039383736353433323130292827267677787980818283848586878889909192939495969798991007574737271706968676665646362616059585756555453525

Strany 55

4CBADE21 3KFGHJ5 76 98 10Bottom ViewTRSTTCKTDITDO TMSEMU0EMU1VDD3VFLTEST1TEST2XCLKOUTXCLKINX1X2XRSGPIO0GPIO1GPIO2 GPIO3 GPIO4GPIO5GPIO6GPIO7GPIO9 GPIO

Strany 56

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 57 - Peripherals 57

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 58 - 4.3 Hi-Resolution PWM (HRPWM)

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 59 - Peripherals 59

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 60 - Value Register

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 61

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 62

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 63 - Peripherals 63

INT[12:1]Real-Time JTAG(TDI, TDO, TRST, TCK,TMS, EMU0, EMU1)C28x CPU(100 MHz)NMI, INT13Memory BusINT14SYSCLKOUTRSCLKIN12-Bit ADCADCSOCA/BSOCA/B16 Chan

Strany 64

0x00 0000Block StartAddressData SpaceProg SpaceM0 Vector − RAM (32 x 32)(Enabled if VMAP = 0)M1 SARAM (1K y 16)0x00 0400Peripheral Frame 00x00 08000x0

Strany 65

0x00 0000Block StartAddressData SpaceProg SpaceM0 SARAM (1K y 16)M1 SARAM (1K y 16)0x00 0400Peripheral Frame 00x00 08000x00 0D00Peripheral Frame 1(pro

Strany 66

0x00 0000Block StartAddressData Space0x00 04000x00 08000x00 0D000x00 60000x00 70000x00 80000x00 90000x00 A0000x3D 78000x3D 7C000x3F 7FF80x3F 80000x3F

Strany 67 - 4.6.2 ADC Registers

0x00 0000Block StartAddress0x00 04000x00 08000x00 0D000x00 60000x00 70000x00 80000x00 90000x3D 78000x3F 00000x3F 7FF80x3F 80000x3F 90000x3F F0000x3F F

Strany 68

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 69

0x00 0000Block StartAddress0x00 04000x00 08000x00 0D000x00 60000x00 70000x00 80000x00 90000x3D 78000x3F 40000x3F 7FF80x3F 80000x3F 90000x3F F0000x3F F

Strany 70

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 71

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 72 - Table 4-7. CAN Register Map

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 73 - Peripherals 73

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 74

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 75 - Peripherals 75

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 76

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 77 - Table 4-11. SPI-B Registers

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 78 - Table 4-13. SPI-D Registers

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 79 - Peripherals 79

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 80

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 81 - Table 4-14. I2C-A Registers

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 82 - 4.11 GPIO MUX

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 83 - Table 4-15. GPIO Registers

XINT2C28CPUCPUTIMER2(ReservedforDSP/BIOS)CPUTIMER0WatchdogPeripherals(SPI,SCI,I2C,eCAN,ePWM,eCAP,eQEP,ADC)TINT0InterruptControlXNMICR(15

Strany 84

INT12MUXINT11INT2INT1CPU(Enable)(Flag)INTxINTx.8PIEIERx(8:1) PIEIFRx(8:1)MUXINTx.7INTx.6INTx.5INTx.4INTx.3INTx.2INTx.1FromPeripherals orExternalInterr

Strany 85

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 86 - 5 Device Support

PLLX1X2PowerModesControlWatchdogBlock28xCPUPeripheral BusLow-Speed PeripheralsSCI-A/B, SPI-A/B/C/DPeripheralRegistersHigh-Speed PrescalerLow-Speed Pre

Strany 87

X1XCLKIN (3.3-V clock input)On chiposcillatorX2xorPLLSTS[OSCOFF]OSCCLKPLLVCOCLK4-bit PLL Select (PLLCR)OSCCLK or VCOCLKCLKIN OSCCLK0PLLSTS[PLLOFF]nn ≠

Strany 88 - 5.2 Documentation Support

External Clock Signal (Toggling 0−VDDIO)XCLKINX2NCX1External Clock Signal (Toggling 0−VDD)XCLKINX2NCX1CL1X2X1CrystalCL2XCLKINTMS320F2809, TMS320F2808,

Strany 89 - Device Support 89

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 90

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 91 - Device Support 91

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 92

/512OSCCLKWDCR (WDPS(2:0))WDCLKWDCNTR(7:0)WDKEY(7:0)Good Key1 0 1WDCR (WDCHK(2:0))BadWDCHKKeyWDCR (WDDIS)Clear CounterSCSR (WDENINT)WatchdogPrescalerG

Strany 93 - 6 Electrical Specifications

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 94

BorrowResetTimer ReloadSYSCLKOUTTCR.4(Timer Start Status)TINT16-Bit Timer Divide-Down TDDRH:TDDR32-Bit Timer PeriodPRDH:PRD32-Bit CounterTIMH:TIM16-Bi

Strany 95 - 6.4 Current Consumption

INT1toINT12INT14C28xTINT2TINT0PIECPU-TIMER0CPU-TIMER2(ReservedforDSP/BIOS)INT13TINT1CPU-TIMER1XINT13TMS320F2809, TMS320F2808, TMS320F2806TMS320F28

Strany 96

PIETZ1 to TZ6Peripheral BusePWM1 moduleePWM2 moduleePWMx moduleEPWM1SYNCIEPWM2SYNCIEPWM2SYNCOEPWMxSYNCIEPWMxSYNCOADCGPIOMUXEPWM1SYNCIEPWM1SYNCOADCSOCx

Strany 97 - SYSCLKOUT

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 98 - 100-MHz SYSCLKOUT

CTR = PRDTBPRD Shadow (16)TBPRD Active (16)CounterUp/Down(16-Bit)TBCNTActive (16)TBCTL[PHSEN]TBCTL[SWFSYNC](Software-Forced Sync)EPWMxSYNCICTR = ZEROC

Strany 99

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 100

TSCTR(counter−32 bit)RSTCAP1(APRD active)LDCAP2(ACMP active)LDCAP3(APRD shadow)LDCAP4(ACMP shadow)LDContinuous /OneshotCapture ControlLD1LD2LD3LD4323

Strany 101 - Device Power Vs SYSCLKOUT

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 102 - Submit Documentation Feedback

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 103 - 6.6.2 Test Load Circuit

QWDTMRQWDPRD16QWDOGUTIMEQUPRDQUTMR32UTOUTWDTOUTQuadraturecapture unit(QCAP)QCPRDLATQCTMRLAT16QFLGQEPSTSQEPCTLRegistersused bymultiple unitsQCLKQDIRQIQ

Strany 104 - 6.6.3 Device Clock Table

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 105

Digital Value + 0,Digital Value + 4096 Input Analog Voltage * ADCLO3when input ≤ 0 Vwhen 0 V < input < 3 Vwhen input ≥ 3 VDigital Value + 4095,

Strany 106 - 6.8 Power Sequencing

Result RegistersEPWMSOCBS/WGPIO/XINT2_ADCSOCEPWMSOCAS/WSequencer 2Sequencer 1SOCSOCADC Control Registers70B7h70B0h70AFh70A8hResult Reg 15Result Reg 8R

Strany 107 - Figure 6-8. Power-on Reset

ADCINA[7:0]ADCINB[7:0]ADCLOADCREFINADC External Current Bias ResistorADCRESEXTADCREFPVDD1A18VDD2A18VSS1AGNDVSS2AGNDVDDAIOVSSAIOVDDA2VSSA2ADC Reference

Strany 108 - Figure 6-9. Warm Reset

ADCINA[7:0]ADCINB[7:0]ADCLOADCREFINADC External Current Bias Resistor ADCRESEXTADCREFPVDD1A18VDD2A18VSS1AGNDVSS2AGNDVDDAIOVSSAIOVDDA2VSSA2ADC Referenc

Strany 109 - 6.9.1 GPIO - Output Timing

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 110 - 6.9.2 GPIO - Input Timing

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 111 - XINT2_ADCSOC signal as well

Mailbox RAM(512 Bytes)32-Message Mailboxof 4 × 32-Bit WordsMemory ManagementUnitCPU Interface,Receive Control Unit,Timer Management UniteCAN Memory(51

Strany 112

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 113

Mailbox Enable − CANMEMailbox Direction − CANMDTransmission Request Set − CANTRSTransmission Request Reset − CANTRRTransmission Acknowledge − CANTAAbo

Strany 114

Mailbox Enable − CANMEMailbox Direction − CANMDTransmission Request Set − CANTRSTransmission Request Reset − CANTRRTransmission Acknowledge − CANTAAbo

Strany 115 - 6.10.2 Trip-Zone Input Timing

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 116

Baud rate =LSPCLK16LSPCLK(BRR ) 1) * 8when BRR ≠ 0Baud rate = when BRR = 0Max bit rate +100 MHz16+ 6.25 106bńsMax bit rate +60 MHz16+ 3.75 106bńsT

Strany 117

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 118 - Table 6-33. I2C Timing

TX FIFO _0LSPCLKWUTFrame Format and ModeEven/Odd EnableParitySCI RX Interrupt select logicBRKDTRXRDYSCIRXST.6SCICTL1.38SCICTL2.1RX/BK INT ENASCIRXDSCI

Strany 119 - (1) (2) (3) (4) (5)

Baud rate =LSPCLK4LSPCLK(SPIBRR ) 1)when SPIBRR = 3 to 127Baud rate = when SPIBRR = 0,1, 2TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F280

Strany 120

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 121

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 122

SSPICTL.0SPI INT FLAGSPI INTENASPISTS.6SClockPolarityTalkLSPCLK456 123 00123SPI Bit RateState ControlSPIRXBUFBuffer RegisterClockPhaseReceiverOverrun

Strany 123 - 6.10.6 SPI Slave Mode Timing

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 124 - (1) (2) (3) (4)

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 125 - variation ±4 LSB

SYSRSData[16]SYSCLKOUTData[16]Addr[16]ControlI2CINT1AI2CINT2AC28X CPUGPIOMUXI2C−ASystem ControlBlockI2CAENCLKPIEBlockSDAASCLAPeripheral BusTMS320F2809

Strany 126

GPxDAT (read)InputQualificationGPxMUX1/2High ImpedanceOutput ControlGPIOx pinXRS0 = Input, 1 = OutputLow PowerModes BlockGPxDIR (latch)Peripheral 2 In

Strany 127

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 128

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 129

GPyCTRL RegSYNCSYSCLKOUTQualificationInput Signal Qualified By 3 or 6 SamplesGPIOxTime between samplesGPxQSELNumber of SamplesTMS320F2809, TMS320F2808

Strany 130 - SINAD * 1.76

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 131 - 6.12 Flash Timing

PREFIXTMS 320 F 28015 PZTMX = Experimental DeviceTMP = Prototype DeviceTMS = Qualified DeviceDEVICE FAMILY320 = TMS320E DSP FamilyTECHNOLOGYPACKAGE TY

Strany 132 - 6.13 ROM Timing (C280x only)

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 133 - 7.1 Migration Issues

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 134 - 8 Revision History

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 135 - 9 Mechanical Data

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 136

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 137 - PACKAGE OPTION ADDENDUM

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 138

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 139

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 140

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 141 - MECHANICAL DATA

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 142

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Strany 143 - MECHANICAL DATA

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Strany 144 - IMPORTANT NOTICE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

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