Texas Instruments TMS320DM643x Uživatelský manuál

TMS320DM643x DMPDSP SubsystemReference GuideLiterature Number: SPRU978EMarch 2008

TMS320C6000, C6000 are trademarks of Texas Instruments.Read This First10 SPRU978E – March 2008Submit Documentation Feedback

Chapter 1SPRU978E – March 2008IntroductionTopic ... Pag

www.ti.com1.1 Introduction1.2 Block DiagramJTAG InterfaceSystem ControlPLLs/Clock GeneratorInputClock(s)Power/Sleep ControllerPin MultiplexingDSP Subs

www.ti.com1.3 DSP Subsystem in TMS320DM643x DMP1.3.1 Components of the DSP SubsystemDSP Subsystem in TMS320DM643x DMPIn the DM643x DMP, the DSP subsys

Introduction 14 SPRU978E – March 2008Submit Documentation Feedback

Chapter 2SPRU978E – March 2008TMS320C64x+ MegamoduleTopic ...

www.ti.com2.1 Introduction2.2 TMS320C64x+ CPUIntroductionThe C64x+ Megamodule (Figure 2-1 ) consists of the following components:• TMS320C64x+ CPU• In

www.ti.comCache controlMemory protectBandwidth mgmtL1PRAM/cache256Bandwidth mgmtMemory protectCache control256L2256RAM/CacheROM256Instruction fetchfil

www.ti.com2.3 Memory Controllers2.3.1 L1P ControllerMemory ControllersThe C64x+ Megamodule implements a two-level internal cache-based memory architec

www.ti.comC64x+ CPUFetch Path Data PathWriteBufferL1DCacheL1DSRAML1 DataL1PCacheL1PSRAML1 ProgramL2 CacheL2 SRAML2 Unified Data/Program MemoryExternal

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www.ti.com2.3.2 L1D Controller2.3.3 L2 ControllerMemory ControllersThe L1D controller is the hardware interface between level 1 data memory (L1D memor

www.ti.com2.3.4 External Memory Controller (EMC)2.3.5 Internal DMA (IDMA)Memory ControllersThe external memory controller (EMC) is the hardware interf

www.ti.com2.4 Internal Peripherals2.4.1 Interrupt Controller (INTC)2.4.2 Power-Down Controller (PDC)Internal PeripheralsThis C64x+ Megamodule includes

www.ti.com2.4.3 Bandwidth ManagerInternal PeripheralsThe bandwidth manager provides a programmable interface for optimizing bandwidth among therequest

TMS320C64x+ Megamodule24 SPRU978E – March 2008Submit Documentation Feedback

Chapter 3SPRU978E – March 2008System MemoryTopic ... Pa

www.ti.com3.1 Memory Map3.1.1 DSP Internal Memory (L1P, L1D, L2)3.1.2 External Memory3.1.3 Internal Peripherals3.1.4 Device PeripheralsMemory MapRefer

www.ti.com3.2 Memory Interfaces Overview3.2.1 DDR2 External Memory Interface3.2.2 External Memory Interface3.2.2.1 Asynchronous EMIF Interface3.2.2.2

System Memory28 SPRU978E – March 2008Submit Documentation Feedback

Chapter 4SPRU978E – March 2008Device ClockingTopic ...

ContentsPreface ... 91 Int

www.ti.com4.1 Overview4.2 Clock Domains4.2.1 Core DomainsOverviewThe DM643x DMP requires one primary reference clock. The primary reference clock can

www.ti.comDSP SubsystemSYSCLK1SYSCLK3SCREDMAVPFEVPBEDACsDDR2 PHYDDR2 VTPDDR2 MemorycontrollerPLLDIV2 (/10)PLLDIV1 (/2)BPDIVPLL Controller 2PLL Control

www.ti.com4.2.2 Core Frequency FlexibilityClock DomainsThe core frequency domain clocks are supplied by the PLL controller 1 (PLLC1). These domain clo

www.ti.com4.2.3 DDR2/EMIF ClockClock DomainsThe DDR2 interface has a dedicated clock driven from PLL2. This is a separate clock system from thePLL1 cl

www.ti.com4.2.4 I/O DomainsClock DomainsThe I/O domains refer to the frequencies of the peripherals that communicate through device pins. Inmany cases

www.ti.com4.2.5 Video Processing Back End3201012PLLDIV2CLK54PLL2DDR_CLKx2PCLKVPBECLKMXICLK_VENCCLK_DAC10venc_sclk_encCG OSDVENCDACsvenc_div2venc_sclk_

www.ti.comClock DomainsTable 4-6. Possible Clocking ModesVPSS_CLKCTL.MUXSEL Bit Clocking Mode Description0 MXI mode Both the VENC and the DAC get thei

Chapter 5SPRU978E – March 2008PLL ControllerTopic ... P

www.ti.com5.1 PLL Module5.2 PLL1 ControlPLL ModuleThe DM643x DMP has two PLLs (PLL1 and PLL2) that provide clocks to different parts of the system.PLL

www.ti.comPLLDIV1(/1)PLLDIV3(/6)PLLDIV2(/3)SYSCLK1(CLKDIV1Domain)SYSCLK3(CLKDIV6Domain)SYSCLK2(CLKDIV3Domain)10PLLMPLL01BPDIVCLKMODECLKINOSCINPL

5.3.2 Steps for Changing PLL2 Frequency ... 445.4 PLL Controller Registers ...

www.ti.com5.2.2.1 Initialization to PLL Mode from PLL Power DownPLL1 ControlIf the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), you must

www.ti.com5.2.2.2 Changing PLL MultiplierPLL1 ControlIf the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization

www.ti.com5.2.2.3 Changing SYSCLK DividersPLL1 ControlThis section discusses the software sequence to change the SYSCLK dividers. The SYSCLK dividerch

www.ti.com5.3 PLL2 ControlPLLDIV2 (/10)PLLDIV1 (/2)10PLLMPLL01BPDIVCLKMODECLKINOSCINPLLENPLL2_SYSCLK2(VPSS−VPBE)PLL2_SYSCLK1(DDR2 PHY)PLL2_SYSCLKBP(DD

www.ti.com5.3.2 Steps for Changing PLL2 Frequency5.3.2.1 DDR2 Considerations When Modifying PLL2 Frequency5.3.2.1.1 PLL2 Frequency Change Steps When D

www.ti.com5.3.2.2 Initialization to PLL Mode from PLL Power DownPLL2 ControlIf the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), you must

www.ti.com5.3.2.3 Changing PLL MultiplierPLL2 ControlIf the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization

www.ti.com5.3.2.4 Changing SYSCLK DividersPLL2 ControlThis section discusses the software sequence to change the SYSCLK dividers. The SYSCLK dividerch

www.ti.com5.4 PLL Controller RegistersPLL Controller RegistersTable 5-3 lists the base address and end address for the PLL controllers. Table 5-4 list

www.ti.com5.4.1 Peripheral ID Register (PID)5.4.2 Reset Type Status Register (RSTYPE)PLL Controller RegistersThe peripheral ID register (PID) is shown

7.3.1 Module Clock ON/OFF ... 797.3.2 Module Clock Frequency Scaling ..

www.ti.com5.4.3 PLL Control Register (PLLCTL)PLL Controller RegistersThe PLL control register (PLLCTL) is shown in Figure 5-5 and described in Table 5

www.ti.com5.4.4 PLL Multiplier Control Register (PLLM)5.4.5 PLL Controller Divider 1 Register (PLLDIV1)PLL Controller RegistersThe PLL multiplier cont

www.ti.com5.4.6 PLL Controller Divider 2 Register (PLLDIV2)5.4.7 PLL Controller Divider 3 Register (PLLDIV3)PLL Controller RegistersThe PLL controller

www.ti.com5.4.8 Oscillator Divider 1 Register (OSCDIV1)PLL Controller RegistersThe oscillator divider 1 register (OSCDIV1) is shown in Figure 5-10 and

www.ti.com5.4.9 Bypass Divider Register (BPDIV)PLL Controller RegistersThe bypass divider register (BPDIV) is shown in Figure 5-11 and described in Ta

www.ti.com5.4.10 PLL Controller Command Register (PLLCMD)5.4.11 PLL Controller Status Register (PLLSTAT)PLL Controller RegistersThe PLL controller com

www.ti.com5.4.12 PLL Controller Clock Align Control Register (ALNCTL)PLL Controller RegistersThe PLL controller clock align control register (ALNCTL)

www.ti.com5.4.13 PLLDIV Ratio Change Status Register (DCHANGE)PLL Controller RegistersThe PLLDIV ratio change status register (DCHANGE) is shown in Fi

www.ti.com5.4.14 Clock Enable Control Register (CKEN)PLL Controller RegistersThe clock enable control register (CKEN) is shown in Figure 5-16 and desc

www.ti.com5.4.15 Clock Status Register (CKSTAT)PLL Controller RegistersThe clock status register (CKSTAT) is shown in Figure 5-17 and described in Tab

List of Figures1-1 TMS320DM643x DMP Block Diagram ... 122-1 TMS320C64x+

www.ti.com5.4.16 SYSCLK Status Register (SYSTAT)PLL Controller RegistersThe SYSCLK status register (SYSTAT) is shown in Figure 5-18 and described in T

Chapter 6SPRU978E – March 2008Power and Sleep ControllerTopic ...

www.ti.com6.1 Introductiondsp local resetdsp module resetdsp clockDSPdsp powerperipheral powerperipheral module resetMODxperipheral clockAlways ondoma

www.ti.com6.2 Power Domain and Module TopologyPower Domain and Module TopologyThe DM643x DMP includes one power domain--the AlwaysOn power domain. The

www.ti.com6.3 Power Domain and Module States6.3.1 Power Domain States6.3.2 Module StatesPower Domain and Module StatesNote: The effects of DSP local r

www.ti.com6.3.3 Local Reset6.4 Executing State Transitions6.4.1 Power Domain State Transitions6.4.2 Module State TransitionsExecuting State Transition

www.ti.com6.5 IcePick Emulation Support in the PSC6.6 PSC Interrupts6.6.1 Interrupt EventsIcePick Emulation Support in the PSCThe PSC supports IcePick

www.ti.com6.6.1.1 Module State Emulation Events6.6.1.2 Local Reset Emulation Events6.6.2 Interrupt RegistersPSC InterruptsThe DM643x DMP is a single-p

www.ti.com6.6.3 Interrupt Handling6.7 PSC RegistersPSC RegistersHandle the PSC interrupts as described in the following procedure:First, enable the in

www.ti.com6.7.1 Peripheral Revision and Class Information Register (PID)6.7.2 Interrupt Evaluation Register (INTEVAL)PSC RegistersThe peripheral revis

List of Tables4-1 System Clock Modes and Fixed Ratios for Core Clock Domains... 304-2 Example PLL1 Fr

www.ti.com6.7.3 Module Error Pending Register 1 (MERRPR1)6.7.4 Module Error Clear Register 1 (MERRCR1)PSC RegistersThe module error pending register 1

www.ti.com6.7.5 Power Domain Transition Command Register (PTCMD)6.7.6 Power Domain Transition Status Register (PTSTAT)PSC RegistersThe power domain tr

www.ti.com6.7.7 Power Domain Status 0 Register (PDSTAT0)PSC RegistersThe power domain status n register (PDSTAT0) is shown in Figure 6-8 and described

www.ti.com6.7.8 Power Domain Control 0 Register (PDCTL0)PSC RegistersThe power domain control n register (PDCTL0) is shown in Figure 6-9 and described

www.ti.com6.7.9 Module Status n Register (MDSTATn)PSC RegistersThe module status n register (MDSTAT0-MDSTAT39) is shown in Figure 6-10 and described i

www.ti.com6.7.10 Module Control n Register (MDCTLn)PSC RegistersThe module control n register (MDCTL0-MDCTL39) is shown in Figure 6-11 and described i

Power and Sleep Controller76 SPRU978E – March 2008Submit Documentation Feedback

Chapter 7SPRU978E – March 2008Power ManagementTopic ...

www.ti.com7.1 Overview7.2 PSC and PLLC OverviewOverviewIn many applications, there may be specific requirements to minimize power consumption for both

www.ti.com7.3 Clock Management7.3.1 Module Clock ON/OFF7.3.2 Module Clock Frequency Scaling7.3.3 PLL Bypass and Power DownClock ManagementThe module c

List of Tables8 SPRU978E – March 2008Submit Documentation Feedback

www.ti.com7.4 DSP Sleep Mode Management7.4.1 DSP Sleep Modes7.4.2 DSP Module Clock ON/OFF7.4.2.1 DSP Module Clock ONDSP Sleep Mode ManagementThe C64x+

www.ti.com7.4.2.2 DSP Module Clock Off7.5 3.3 V I/O Power Down7.6 Video DAC Power Down3.3 V I/O Power DownIn the clock Disable state, the DSP’s module

Power Management82 SPRU978E – March 2008Submit Documentation Feedback

Chapter 8SPRU978E – March 2008Interrupt ControllerThe C64x+ Megamodule includes an interrupt controller (INTC) to manage CPU interrupts. The interrupt

Interrupt Controller84 SPRU978E – March 2008Submit Documentation Feedback

Chapter 9SPRU978E – March 2008System ModuleTopic ... Pa

www.ti.com9.1 Overview9.2 Device Identification9.3 Device Configuration9.3.1 Pin Multiplexing Control9.3.2 Device Boot Configuration StatusOverviewThe

www.ti.com9.4 3.3 V I/O Power-Down Control9.5 Peripheral Status and Control9.5.1 Timer Control9.5.2 VPSS Clock and DAC Control9.5.3 DDR2 VTP Control9.

www.ti.com9.6 Bandwidth Management9.6.1 Bus Master DMA Priority ControlBandwidth ManagementIn order to determine allowed connections between masters a

www.ti.com9.6.2 EDMA Transfer Controller Configuration9.7 Boot ControlBoot ControlEach switched central resource (SCR) performs prioritization based o

PrefaceSPRU978E – March 2008Read This FirstAbout This ManualThis document describes the DSP subsystem in the TMS320DM643x Digital Media Processor (DMP

System Module90 SPRU978E – March 2008Submit Documentation Feedback

Chapter 10SPRU978E – March 2008ResetTopic ... Page10.1

www.ti.com10.1 Overview10.2 Reset Pins10.3 Device Configurations at ResetOverviewThere are different types of reset in the TMS320DM643x DMP. The types

www.ti.com10.4 DSP Reset10.4.1 DSP Local Reset10.4.2 DSP Module Reset10.4.2.1 Software Reset Disable (SwRstDisable)DSP ResetNote: The effects of DSP l

www.ti.com10.4.2.2 Synchronous Reset (SyncReset)DSP Reset• Host: Assert the DSP local reset (Optional)– Clear the LRST bit in MDCTL39 to 0. This step

Chapter 11SPRU978E – March 2008Boot ModesThe TMS320DM643x DMP can boot from either asynchronous EMIF/NOR Flash directly or from internalboot ROM, as d

Boot Modes96 SPRU978E – March 2008Submit Documentation Feedback

Appendix ASPRU978E – March 2008Revision HistoryTable A-1 lists the changes made since the previous version of this document.Table A-1. Document Revisi

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme