Texas Instruments TMS320C6202 Uživatelský manuál stáhnout pdf (Strana 62)

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for FSR when GSYNC = 1 (see Figure 41)

NO.

’C6202-200

’C6202-233

’C6202-250

UNIT

MIN MAX

1 t

su(FRH-CKSH)

Setup time, FSR high before CLKS high 4 ns

2 t

h(CKSH-FRH)

Hold time, FSR high after CLKS high 4 ns

CLKS

FSR external

CLKR/X (no need to resync)

CLKR/X(needs resync)

Figure 41. FSR Timing When GSYNC = 1

ADVANCE INFORMATION

1 2 ... 57 58 59 60 61 62 63 64 65 66 67 ... 73 74

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Texas Instruments TMS320C6202 Uživatelský manuál Strana 62