Texas Instruments PCI7421 manuály

Texas instruments PCI7421 Uživatelský manuál (299 strany)

Značka: Texas-instruments | Kategorie: ne | Velikost: 1.26 MB |

Angličtina

Tabulka s obsahem

Data Manua

1

Contents

3

5−19.

6

5−23. .

6

List of Illustrations

12

List of Tables

13

Table Title Page

18

1 Introduction

19

1.1.2 PCI7421 Controller

20

1.1.3 PCI7611 Controller

20

1.1.4 PCI7411 Controller

21

1.1.7 Power Switch Interface

21

1.2 Features

22

1.3 Related Documents

23

1.4 Trademarks

24

1.5 Terms and Definitions

25

1.6 Ordering Information

25

2 Terminal Descriptions

27

MFUNC0 MFUNC5

28

MFUNC2 MFUNC4MFUNC3

28

I/O TTLI1 TTLO1

41

I/O PCII3 PCIO3 V

43

Table 2−16. SD/MMC Terminals

53

3.1 Power Supply Sequencing

57

3.2 I/O Characteristics

58

3.3 Clamping Voltages

58

3.4.2 Device Resets

59

3.4.3 Serial EEPROM I

59

1 controller to route the SDA

60

3.5 PC Card Applications

61

Section 4.31):

62

3.5.5 Power Switch Interface

64

3.6 Serial EEPROM Interface

67

Table 3−9. EEPROM Loading Map

70

00h = No MINI ROM

71

2Bh OHCI 24h, GUIDHi, byte 0

71

3.8 Power Management Overview

76

3.8.6 Suspend Mode

79

3.8.8 Ring Indicate

80

3.8.9 PCI Power Management

81

3.8.11 ACPI Support

83

3.9.2 Crystal Selection

87

3.9.3 Bus Reset

88

4.2 Vendor ID Register

92

02h (Functions 0 and 1)

93

4.4 Command Register

94

4.5 Status Register

95

4.6 Revision ID Register

96

4.7 Class Code Register

96

4.8 Cache Line Size Register

96

4.9 Latency Timer Register

97

4.10 Header Type Register

97

4.11 BIST Register

97

see Section 4.25)

99

4.15 PCI Bus Number Register

100

1Bh (Functions 0, 1)

101

1Ch, 24h

101

20h, 28h

102

2Ch, 34h

102

4.23 Interrupt Line Register

103

4.24 Interrupt Pin Register

104

4.25 Bridge Control Register

105

40h (Functions 0, 1)

106

4.27 Subsystem ID Register

107

4.29 System Control Register

108

4.30 MC_CD Debounce Register

110

4.31 General Control Register

111

4.37 Retry Status Register

117

4.38 Card Control Register

118

4.39 Device Control Register

119

4.40 Diagnostic Register

120

4.41 Capability ID Register

121

A2h (Functions 0, 1)

122

A4h (Functions 0, 1)

123

A6h (Functions 0, 1)

124

A7h (functions 0, 1)

124

4.47 Serial Bus Data Register

125

B2h (function 0)

126

B3h (function 0)

127

Type: Read/Write, Read-only

133

Type: Read-only

134

Type: Read-only, Read/Write

135

Type: Read/Write

136

Default: 00h

137

I/O window control

140

Bit 7 6 5 4 3 2 1 0

143

Type RW RW RW RW RW RW RW RW

143

Default 0 0 0 0 0 0 0 0

143

Type RW RW RW RW RW RW RW R

152

6.1 Socket Event Register

154

6.2 Socket Mask Register

155

CardBus Socket Address + 0Ch

157

6.5 Socket Control Register

159

CardBus Socket Address + 20h

160

7.1 Vendor ID Register

162

7.2 Device ID Register

162

7.3 Command Register

163

7.4 Status Register

164

7.14 Interrupt Line Register

170

7.15 Interrupt Pin Register

170

7.17 OHCI Control Register

171

7.22 PCI PHY Control Register

175

7.26 GPIO Control Register

179

8 OHCI Registers

181

8.1 OHCI Version Register

184

8.2 GUID ROM Register

185

8.4 CSR Data Register

186

8.5 CSR Compare Register

187

8.6 CSR Control Register

187

8.9 Bus Options Register

189

8.10 GUID High Register

190

8.11 GUID Low Register

190

8.15 Vendor ID Register

192

50h set register

193

8.18 Self-ID Count Register

195

70h set register

196

78h set register

197

8.21 Interrupt Event Register

198

8.22 Interrupt Mask Register

200

90h set register

202

98h set register

203

A0h set register

204

A8h set register

205

8.31 Link Control Register

208

100h set register

212

108h set register

214

110h set register

215

118h set register

217

180h set register [ATRQ]

218

18Ch [ATRQ]

219

200h + (16 * n) set register

220

20Ch + (16 * n)

221

400h + (32 * n) set register

221

40Ch + (32 * n)

223

410Ch + (32 * n)

224

9 TI Extension Registers

225

A80h set register

226

9.4 Link Enhancement Register

228

9.5 Timestamp Offset Register

229

10 PHY Register Configuration

231

10.2 Port Status Register

234

10.5 Power-Class Programming

237

11.1 Vendor ID Register

240

11.2 Device ID Register

240

11.3 Command Register

241

11.4 Status Register

242

11.12 Interrupt Line Register

246

11.13 Interrupt Pin Register

246

11.14 Minimum Grant Register

247

1.21). When this bit is set

249

15−0 SubsystemVendorID RW

252

11.23 Diagnostic Register

253

12.1 Vendor ID Register

256

12.2 Device ID Register

256

12.3 Command Register

257

12.4 Status Register

258

12.12 Interrupt Line Register

262

12.13 Interrupt Pin Register

263

12.14 Minimum Grant Register

263

12.24 Diagnostic Register

269

13.1 Vendor ID Register

274

13.2 Device ID Register

274

13.3 Command Register

275

13.4 Status Register

276

14h, 18h, 1Ch, and 20h

279

13.13 Interrupt Line Register

280

13.14 Interrupt Pin Register

281

13.15 Minimum Grant Register

281

14 Electrical Characteristics

291

(unless otherwise noted)

295

15 Mechanical Information

297

PACKAGE OPTION ADDENDUM

299

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