Texas Instruments TMS320DM646X DMSOC Uživatelský manuál stáhnout pdf (Strana 59)

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Registers

Table 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions (continued)

Bit Field Value Description

0 ATMCLR Asynchronous Timeout Mask Clear. This bit determines whether or not the asynchronous timeout

interrupt is enabled. Writing a 1 to this bit clears this bit and the ATMSET bit in the EMIF interrupt mask

set register (EIMSR), and disables the asynchronous timeout interrupt. To set this bit, a 1 must be

written to the ATMSET bit in EIMSR.

0 Indicates that the asynchronous timeout interrupt is disabled. Writing a 0 has no effect.

1 Indicates that the asynchronous timeout interrupt is enabled. Writing a 1 clears this bit and the ATMSET

bit in EIMSR.

SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF)

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Texas Instruments TMS320DM646X DMSOC Uživatelský manuál Strana 59