Texas-instruments TMS320C3x Uživatelský manuál stáhnout pdf (Strana 736)

100

101

Glossary

D-3

Glossary

data size: The number of bits (8, 16, or 32) used to represent a particular

number.

decode phase: The phase of the pipeline in which the instruction is decoded

(identified).

DMA coprocessor: A peripheral that transfers the contents of memory loca-

tions independently of the processor (except for initialization).

DMA controller: See DMA coprocessor.

DP: See data-page pointer.

dual-access RAM: Memory that can be accessed twice in a single clock

cycle. For example, code that can read from and write to a RAM in one

clock cycle.

external interrupt: A hardware interrupt triggered by a pin.

extended-precision floating-point format: A 40-bit representation of a

floating-point number with a 32-bit mantissa and an 8-bit exponent.

extended-precision register: A 40-bit register used primarily for extended-

precision floating-point calculations. Floating-point operations use bits

39–0 of an extended-precision register. Integer operations, however, use

only bits 31–0.

FIFO buffer:

First-in, first-out buffer.

A portion of memory in which data is

stored and then retrieved in the same order in which it was stored. Thus,

the first word stored in this buffer is retrieved first.

hardware interrupt: An interrupt triggered through physical connections

with on-chip peripherals or external devices.

hit: A condition in which, when the processor fetches an instruction, the

instruction is available in the cache.

1 2 ... 731 732 733 734 735 736 737 738 739 740 741 ... 756 757

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