Texas-instruments Digital Signal Processor SM320F2812-HT Uživatelský manuál stáhnout pdf (Strana 108)

c(SPC)

+ SPI clock cycle time +

LSPCLK

(SPIBRR ) 1)

+ t

c(LCO)

+ LSPCLK cycle time

GPIOxn

XCLKOUT

w(GPI)

(2)

SM320F2812-HT

SGUS062B–JUNE 2009 – REVISED JUNE 2011

www.ti.com

Figure 6-23. General-Purpose Input Timing

NOTE

The pulse width requirement for general-purpose input is applicable for the XBIO and

ADCSOC pins as well.

6.19 SPI Master Mode Timing

Table 6-21. SPI Master Mode External Timing (Clock Phase = 0)

(1) (2) (3)

SPI WHEN (SPIBRR + 1) SPI WHEN (SPIBRR + 1)

IS EVEN OR IS ODD AND

NO. UNIT

SPIBRR = 0 OR 2 SPIBRR > 3

MIN MAX MIN MAX

1 t

c(SPC)M

Cycle time, SPICLK 4t

c(LCO)

128t

c(LCO)

127t

c(LCO)

Pulse duration, SPICLK high

w(SPCH)M

0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

0.5t

c(SPC)M

– 0.5t

c(LCO)

– 10 0.5t

c(SPC)M

– 0.5t

c(LCO)

(clock polarity = 0)

(4)

Pulse duration, SPICLK low

w(SPCL)M

0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

0.5t

c(SPC)M

– 0.5t

c(LCO)

– 10 0.5t

c(SPC)M

– 0.5t

c(LCO)

(clock polarity = 1)

Pulse duration, SPICLK low

w(SPCL)M

0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

0.5t

c(SPC)M

+ 0.5t

c(LCO)

– 10 0.5t

c(SPC)M

+ 0.5t

c(LCO)

(clock polarity = 0)

(4)

Pulse duration, SPICLK high

w(SPCH)M

0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

0.5t

c(SPC)M

+ 0.5t

c(LCO)

– 10 0.5t

c(SPC)M

+ 0.5t

c(LCO)

(clock polarity = 1)

Delay time, SPICLK high to SPISIMO

d(SPCH-SIMO)M

–10 10 –10 10

valid (clock polarity = 0)

(4)

Delay time, SPICLK low to SPISIMO

d(SPCL-SIMO)M

–10 10 –10 10

valid (clock polarity = 1)

Valid time, SPISIMO data valid after

v(SPCL-SIMO)M

0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

+ 0.5t

c(LCO

) – 10

SPICLK low (clock polarity = 0)

(4)

Valid time, SPISIMO data valid after

v(SPCH-SIMO)M

0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

+ 0.5t

c(LCO)

– 10

SPICLK high (clock polarity = 1)

Setup time, SPISOMI before SPICLK

su(SOMI-SPCL)M

0 0

low (clock polarity = 0)

(4)

Setup time, SPISOMI before SPICLK

su(SOMI-SPCH)M

0 0

high (clock polarity = 1)

Valid time, SPISOMI data valid after

v(SPCL-SOMI)M

0.25t

c(SPC)M

– 10 0.5t

c(SPC)M

– 0.5t

c(LCO)

– 10

SPICLK low (clock polarity = 0)

(4)

Valid time, SPISOMI data valid after

v(SPCH-SOMI)M

0.25t

c(SPC)M

– 10 0.5t

c(SPC)M

– 0.5t

c(LCO)

– 10

SPICLK high (clock polarity = 1)

(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.

(3) Not production tested.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Submit Documentation Feedback

Product Folder Link(s): SM320F2812-HT

1 2 ... 103 104 105 106 107 108 109 110 111 112 113 ... 152 153

Komentáře k této Příručce

Žádné komentáře

Texas-instruments Digital Signal Processor SM320F2812-HT Uživatelský manuál Strana 108

Komentáře k této Příručce

Související produkty a manuály pro Hardware Texas-instruments Digital Signal Processor SM320F2812-HT