Texas-instruments Digital Signal Processor SM320F2812-HT Uživatelský manuál stáhnout pdf (Strana 112)

c(SPC)

+ SPI clock cycle time +

LSPCLK

(SPIBRR ) 1)

+ t

c(LCO)

+ LSPCLK cycle time

SPISIMO

SPISOMI

SPICLK

(clock polarity = 1)

SPICLK

(clock polarity = 0)

SPISIMO Data

Must Be Valid

SPISOMI Data Is Valid

SPISTE

(see Note A)

(2)

SM320F2812-HT

SGUS062B–JUNE 2009 – REVISED JUNE 2011

www.ti.com

6.20 SPI Slave Mode Timing

Table 6-23. SPI Slave Mode External Timing (Clock Phase = 0)

(1) (2) (3)

NO. MIN MAX UNIT

12 t

c(SPC)S

Cycle time, SPICLK 4t

c(LCO)

(2)

w(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0) 0.5t

c(SPC)S

– 10 0.5t

c(SPC)S

(4)

w(SPCL)S

Pulse duration, SPICLK low (clock polarity = 1) 0.5t

c(SPC)S

– 10 0.5t

c(SPC)S

w(SPCL)S

Pulse duration, SPICLK low (clock polarity = 0) 0.5t

c(SPC)S

– 10 0.5t

c(SPC)S

(4)

w(SPCH)S

Pulse duration, SPICLK high (clock polarity = 1) 0.5t

c(SPC)

– 10 0.5t

c(SPC)S

Delay time, SPICLK high to SPISOMI valid

d(SPCH-SOMI)S

0.375t

c(SPC)S

– 10

(clock polarity = 0)

(4)

d(SPCL-SOMI)S

Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 0.375t

c(SPC)S

– 10

Valid time, SPISOMI data valid after SPICLK low

v(SPCL-SOMI)S

0.75t

c(SPC)S

(clock polarity = 0)

(4)

Valid time, SPISOMI data valid after SPICLK high

v(SPCH-SOMI)S

0.75t

c(SPC)S

(clock polarity = 1)

su(SIMO-SPCL)S

Setup time, SPISIMO before SPICLK low (clock polarity = 0) 0

(4)

su(SIMO-SPCH)S

Setup time, SPISIMO before SPICLK high (clock polarity = 1) 0

Valid time, SPISIMO data valid after SPICLK low

v(SPCL-SIMO)S

0.5t

c(SPC)S

(clock polarity = 0)

(4)

Valid time, SPISIMO data valid after SPICLK high

v(SPCH-SIMO)S

0.5t

c(SPC)S

(clock polarity = 1)

(1) The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(3) Not production tested.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and

remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.

Figure 6-26. SPI Slave Mode External Timing (Clock Phase = 0)

Submit Documentation Feedback

Product Folder Link(s): SM320F2812-HT

1 2 ... 107 108 109 110 111 112 113 114 115 116 117 ... 152 153

Komentáře k této Příručce

Žádné komentáře

Texas-instruments Digital Signal Processor SM320F2812-HT Uživatelský manuál Strana 112

Komentáře k této Příručce

Související produkty a manuály pro Hardware Texas-instruments Digital Signal Processor SM320F2812-HT