Texas-instruments Digital Signal Processor SM320F2812-HT Uživatelský manuál stáhnout pdf (Strana 126)

Lead 1

Active

Trail

XCLKOUT = XTIMCLK

XCLKOUT = 1/2 XTIMCLK

XA[0:18]

XD[0:15]

XREADY(Synch)

d(XCOHL-XWEL)

d(XCOHL-XWEH)

d(XCOHL-XZCSH)

d(XCOH-XA)

WS (Synch)

XZCS0AND1

, XZCS2,

XZCS6AND7

XRD

XWE

XR/W

d(XCOH-XZCSL)

NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access

to meet this requirement.

B. During alignment cycles, all signals transitions to their inactive state.

C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.

D. For each sample, setup time from the beginning of the access can be calculated as

D = (XWRLEAD + XWRACTIVE + n − 1) t

c(XTIM)

− t

su(XRDYsynchL)XCOHL

where n is the sample number: n = 1, 2, 3 and so forth.

E. Reference for the first sample is with respect to this point

E = (XWRLEAD + XWRACTIVE) t

c(XTIM)

d(XCOH-XRNWL)

d(XCOHL-XRNWH)

en(XD)XWEL

h(XD)XWEH

su(XRDHsynchH)XCOHL

su(XRDYsynchL)XCOHL

DOUT

d(XWEL-XD

)

dis(XD)XRNW

h(XRDYsynchL)

h(XRDYsynchH)XZCSH

= Don’t care. Signal can be high or low during this time.

Legend:

See Note E

See Note D

See

Notes

and

See

Note

e(XRDYsynchH)

SM320F2812-HT

SGUS062B–JUNE 2009 – REVISED JUNE 2011

www.ti.com

Figure 6-33. Write With Synchronous XREADY Access

XTIMING register parameters used for this example:

XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE

0 = XREADY

N/A

(1)

N/A

(1)

N/A

(1)

1 0 ≥ 1 3 ≥ 1

(Synch)

(1) N/A = "Don't care" for this example

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