Texas-instruments Digital Signal Processor SM320F2812-HT Uživatelský manuál stáhnout pdf (Strana 120)

Lead

Active

Trail

d(XCOH-XZCSL)

d(XCOH-XA)

d(XCOHL-XWEL)

d(XCOHL-XWEH)

d(XCOHL-XZCSH)

en(XD)XWEL

h(XD)XWEH

dis(XD)XRNW

XCLKOUT=XTIMCLK

XCLKOUT= 1/2 XTIMCLK

XZCS0AND1, XZCS2,

XZCS6AND7

XA[0:18]

XRD

XWE

XR/W

XD[0:15]

NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle

before an access to meet this requirement.

B. During alignment cycles, all signals transitions to their inactive state.

C. For USEREADY = 0, the external XREADY input signal is ignored.

D. XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles.

d(XCOH-XRNWL)

d(XCOHL-XRNWH)

DOUT

XREADY

d(XWEL-XD)

SM320F2812-HT

SGUS062B–JUNE 2009 – REVISED JUNE 2011

www.ti.com

XTIMING register parameters used for this example:

XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE

≥ 1 ≥ 0 ≥ 0 0 0 N/A

(1)

N/A

(1)

N/A

(1)

N/A

(1)

(1) N/A = "Don't care" for this example

6.24 External Interface Write Timing

Table 6-36. External Memory Interface Write Switching Characteristics

(1)

PARAMETER MIN MAX UNIT

d(XCOH-XZCSL)

Delay time, XCLKOUT high to zone chip-select active low 1 ns

d(XCOHL-XZCSH)

Delay time, XCLKOUT high or low to zone chip-select inactive high –2 3 ns

td(XCOH-XA)

Delay time, XCLKOUT high to address valid 2 ns

d(XCOHL-XWEL)

Delay time, XCLKOUT high/low to XWE low 2 ns

d(XCOHL-XWEH)

Delay time, XCLKOUT high/low to XWE high 2 ns

d(XCOH-XRNWL)

Delay time, XCLKOUT high to XR/W low 1 ns

d(XCOHL-XRNWH)

Delay time, XCLKOUT high/low to XR/W high –2 1 ns

en(XD)XWEL

Enable time, data bus driven from XWE low 0 ns

d(XWEL-XD)

Delay time, data valid after XWE active low 4 ns

h(XA)XZCSH

Hold time, address valid after zone chip-select inactive high

(2)

h(XD)XWE

Hold time, write data valid after XWE inactive high TW–2

(3)

dis(XD)XRNW

Data bus disabled after XR/W inactive high 4 ns

(1) Not production tested.

(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.

(3) TW = Trail period, write access. See Table 6-25.

Figure 6-30. Example Write Access

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